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path: root/src/evergreen_exa.c
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2012-02-06r600-evergreen: use common surface allocator for tiling v11Jerome Glisse
Use libdrm common surface code so mesa,ddx have same idea about tiling surface and what their pitch should be and the alignment constraint. v2 fix remaining issue add new option to conditionaly enable v3 fix fbcon copy and r600 exa copy path v4 fix non tiled path 2D tiling on GPU >= R600, set it to false as default v5 adapt to pixel/element size split of libdrm/radeon v6 update to properly handle falling back to 1d tiled v6 final fix to tile split value on evergreen and newer v7 fix default array mode on r6xx, fix height alignment issue on evergreen v8 fix tile split value v9 add stencil tile split support, simplify dri2 for stencil with evergreen v10 Try to fix xv path regarding tiling. Adapt to libdrm API change. Try to fix case where there is no surface which means non tiled bo. v11 check for proper libdrm Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-01-10EXA/r6xx+: fix rop setting for overlapping copiesAlex Deucher
Need to use GXCopy for the src to temp copy, then the original rop for the temp to dest copy. Noticed by: Frank Huang Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-11-21ddx/evergreen: Fix endian of ALU constantsBenjamin Herrenschmidt
The constants are written directly into a buffer object shared with the card and we "forget" to swap them. This patch fixes it by doing the swap in evergreen_set_alu_consts() in-place (ie, it modifies the buffer), which should be fine with the way we use it in the ddx. This makes everything work fine on my caicos card on a G5 including some quik tests with Xv, gnome3 shell, etc... Thanks a lot to Jerome Glisse for holding my hand through debugging that (and finding the actual bug). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-10-27EXA >= R6xx / KMS: Avoid running out of CS space at inconvenient times.Michel Dänzer
Otherwise we may end up with things not properly set up at the beginning of the next CS. Fixes http://bugs.debian.org/645007 . In contrast to the Composite code for < R6xx, this isn't necessary with UMS, as the draw packet only uses constant space in the indirect buffer, and nothing else can mess with the 3D state between indirect buffers. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-05-24Revert "cayman: add scissors workaround."Alex Deucher
Needs a proper workaround for a hw bug. This reverts commit b77d374b0d11f48c33cfffdb4157c4ec4b05ea15.
2011-05-24cayman: enable all accelDave Airlie
2011-05-24cayman: add scissors workaround.Dave Airlie
wasted a lot of time getting to this.
2011-05-24cayman: first pass at exa/Xv shadersAlex Deucher
Main differences with evergreen: - 4-way rather than 5-way - END_OF_PROGRAM bit removed from CF istructions, use CF_INST_END instead. - MEGA_FETCH* fields removed from VTX commands - no more VC, all fetches go through the TC Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-24kms/cayman: stub out exa supportAlex Deucher
Just fallbacks for now. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-04radeon: add add hw DFS support for fusionDave Airlie
Fusion had a bug setting up the VM on earlier kernels so we need to work around that and only enable accel on a new enough kernel. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-20EXA/Xv: used cached bo tiling flags for accel setup on 6xx+Alex Deucher
This avoids calling into the kernel for each bo in the accel code. This is a follow on to: cc7d1fa39da40a532fcdbe6c7924ca47a879e66a Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-05EXA: Cache BO tiling flags.Michel Dänzer
Calling into the kernel every time is quite expensive, and nobody else should ever change the tiling flags. There's still more to do along the same lines for >= R6xx.
2011-03-16radeon/exa: correct function nameDave Airlie
this corrects the function name so it matches the contents. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-02r6xx+: truncate point sampled coordinatesAlex Deucher
By default the hardware rounds texcoords. However, for point sampled textures, the expected behavior is to truncate. When we have point sampled textures, set the truncate bit in the sampler. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-16kms: EXA/Xv tiling fixesAlex Deucher
- properly set tiling flags for temp surfaces - fix CB non_disp_tiling bits on evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-11kms: evergreen/ni big endian accel supportAlex Deucher
Based on 6xx/7xx patches from Cédric Cano. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-11kms/exa: UTS/DFS base alignment fixesAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-11EXA/r6xx+: properly account for height alignment in copy temp bufferAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10remove EVERGREENSetAccelState()Alex Deucher
It was a duplicate of the R600 variant. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-106xx+: switch to linear aligned rather than linear generalAlex Deucher
linear aligned is supposedly more performant, but more importantly, linear general only works on the CB without slices. The texture blocks technically don't support linear general although, I think linear general gets upgraded to linear aligned in the hw which is why it currently works. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10evergreen/NI: consolidate spi setupAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10evergreen/ni: consolidate CB state handlingAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10kms/r6xx+: clean up pitch/height alignment in EXA UTS/DFSAlex Deucher
2011-02-01kms/r6xx+: fix tiling and pageflipping harderAlex Deucher
Thanks for Michel for final fix. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=33738 for r6xx+ asics. A similar approach for pre-r6xx asics is pending. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-21evergreen: use vb_offset rather than vb_start_op for cbuf offsetAlex Deucher
2011-01-21vbo: remove useless radeon_vb_discard()Alex Deucher
We already reset vb_start_op to -1 in the UMS/KMS ib discard functions.
2011-01-10Merge branch 'kms-pflip' of ↵Alex Deucher
git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati
2010-12-17exa/dfs/ontario: always use the CPU for DFS for nowAlex Deucher
There are issues with rendering to gart memory that haven't been sorted out completely yet.
2010-12-03radeon: remove duplicated defineAlex Deucher
xfixedtofloat macro was defined several times
2010-12-03radeon/exa: fallback for non-affine transformsAlex Deucher
We need to implement a texture lookup with perspective divide for non-affine transforms. For now just fallback. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=31799 although it appears either EXA or the xserver gets this wrong too.
2010-12-01radeon/kms: allow tiled front buffer on 6xx/7xxAlex Deucher
Use UTS/DFS to tile/untile as appropriate for sw access. Also enables pageflipping with tiling enabled.
2010-11-29evergreen: use dot4 for transformsAlex Deucher
2010-11-22Ontario: add workaround for small pixmap issues with DFSAlex Deucher
On past asics these kind a problems were usually due to a bad backend map config. I suspect in this case, and the previous cases it may be related to using linear buffers rather than tiled. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-10-27Fix another stray xfree() call.Michel Dänzer
2010-10-07fix the non-kms buildAlex Deucher
Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=30685
2010-10-04evergreen: use EXACreatePixmap2 if availableAlex Deucher
2010-10-04evergreen: port Karl's UTS/DFS changes to evergreenAlex Deucher
2010-08-23evergreen: use vbo pool for constant buffersAlex Deucher
2010-08-23radeon: move vbo data to a separate structAlex Deucher
this way we can share the vbo code with const buffers
2010-08-20Add initial EXA and Xv support for evergreenAlex Deucher
Based on the r6xx/r7xx code updated for evergreen. Still causes GPU hangs in some cases. We haven't tracked down why yet. Might be related to constant buffer persistence. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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