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2018-07-12Replace 'foo == NULL' with '!foo'Michel Dänzer
Shorter and sweeter. :) (Ported from amdgpu commit e8e688f3852fb06b0c34ed5bce47c9493bcd1613) Acked-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-09Add struct radeon_bufferMichel Dänzer
Inspired by amdgpu, preparation for the following change. For now, this is mostly a wrapper around struct radeon_bo, no functional change intended. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-09EXA: Remove old RADEONEXACreatePixmap hookMichel Dänzer
Not used by any supported version of xserver. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-01-22exa: Accelerate ARGB2101010 picturesFredrik Höglund
Tested by Mario on a Radeon HD 4000 series for the r600 exa path, and on Radeon HD 5770 for the evergreen exa path. Signed-off-by: Fredrik Höglund <fredrik@kde.org> Reviewed-and-Tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-08-30Require xserver >= 1.13Michel Dänzer
xserver 1.13.0 was released on September 6th, 2012, almost 5 years ago. This allows cleaning up a bunch of backwards compatibility code. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-01-07radeon/exa: Always use a scratch surface for UTS to vramAlex Deucher
If we don't, we may hit a buffer that crosses the visible vram boundary resulting in a sigbus when the CPU accesses the buffer beyond the PCI aperture. This will introduce an extra copy in certain cases. This is based on Michel's patch from bug 44099 updated for all asic families. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=44099 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-10-01EXA/evergreen: Paranoia around linear tiling. (v2)Christopher James Halse Rogers
The last two bytes of tiling_mode contain the actual tiling mode; the rest are extra tiling configuration bits. These configuration bits are not necessarily zero for a linear buffer, so mask them out before checking for linearity v2: Also fix up evergreen_textured_videofuncs.c agd5f: remove trailing whitespace Signed-off-by: Christopher James Halse Rogers <raof@ubuntu.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-31EXA/evergreen/ni: replace magic numberGrigori Goronzy
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2013-07-22EXA/evergreen/ni: accelerate PictOpOver with component alphaGrigori Goronzy
Subpixel text rendering is typically done with a solid src and a pixmap mask. Traditionally, this cannot be accelerated in a single pass and requires two passes [1]. However, we can cheat a little with a constant blend color. We can use: const.A = src.A / src.A const.R = src.R / src.A const.G = src.G / src.A const.B = src.B / src.A dst.A = const.A * (src.A * mask.A) + (1 - (src.A * mask.A)) * dst.A dst.R = const.R * (src.A * mask.R) + (1 - (src.A * mask.R)) * dst.R dst.G = const.G * (src.A * mask.G) + (1 - (src.A * mask.G)) * dst.G dst.B = const.B * (src.A * mask.B) + (1 - (src.A * mask.B)) * dst.B This only needs a single source value. src.A is cancelled down in the right places. [1] http://anholt.livejournal.com/32058.html
2013-07-22EXA/evergreen/ni: fast solid pixmap supportGrigori Goronzy
Solid pixmaps are currently implemented with scratch pixmaps, which is slow. This replaces the hack with a proper implementation. The Composite shader can now either sample a src/mask or use a constant value.
2013-07-22EXA/evergreen/ni: optimize non-overlapping CopyGrigori Goronzy
In case dst and src rectangles of a Copy operation in the same surface don't overlap, it is safe to skip the scratch surface. This is a common case.
2013-07-22Fix RADEON_FALLBACK loggingGrigori Goronzy
2013-01-10Drop support for X servers older than 1.7.Michel Dänzer
The main purpose is to drop DRI2 compatibility code paths which are getting awkward to deal with and at this point are probably only tested lightly if at all. xserver 1.7 was released more than 3 years ago, and 1.6.2 was already required before. Mostly mechanical, there's probably potential for more cleanups. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-03radeon: add pixmap sharing hooks.Dave Airlie
This hooks into EXA and the dirty tracking to add sharing and output offload support. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-09-03radeon: add shared support to pixmaps.Dave Airlie
this just adds the interface and shared support to the pixmap. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: drop vb_mc_addr, not needed anymoreDave Airlie
This field is totally unused now, so drop it. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: drop offset member of r600 accel objectDave Airlie
This is always 0 now. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: move macros into radeon.hDave Airlie
Drop separate header file, there isn't many separate macros now. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: drop all UMS/DRI1/XAA/overlay support.Dave Airlie
This overhauls the radeon driver and removes all the old UMS-only code, it drops all the UMS, DRI1, XAA, overlay Xv, video capture, tv tuners There are probably a lot more cleanups that will fall out of this afterwards. So far this is compile/build tested. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-23ati: convert to new screen conversion APIsDave Airlie
The compat header takes care of the old server vs new server. this commit was autogenerated from util/modular/x-driver-screen-scrn-conv.sh Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-04-16EXA: Support acceleration of solid pictures on Evergreen/NI.Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-03-20radeon/kms: add support for TN (trinity) APUsAlex Deucher
- KMS only - Includes full EXA/Xv support Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-02-13radeon: r6xx-eg use linear general when using scratch boJerome Glisse
In path where we need to use scratch bo as temporary area, consider it as linear buffer. Not linear aligned. Fix some case such as in bugs: https://bugs.freedesktop.org/show_bug.cgi?id=45827 Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-08EXA/r6xx+: Only set write domain or read domains, not both. (Bug #43893)Michel Dänzer
Avoids an accounting bug in libdrm_radeon 2.4.31 or older. See https://bugs.freedesktop.org/show_bug.cgi?id=43893 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-02-07radeon: fix tiling for weird resolutionJerome Glisse
Should also fix xv for some case. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-06r600-evergreen: use common surface allocator for tiling v11Jerome Glisse
Use libdrm common surface code so mesa,ddx have same idea about tiling surface and what their pitch should be and the alignment constraint. v2 fix remaining issue add new option to conditionaly enable v3 fix fbcon copy and r600 exa copy path v4 fix non tiled path 2D tiling on GPU >= R600, set it to false as default v5 adapt to pixel/element size split of libdrm/radeon v6 update to properly handle falling back to 1d tiled v6 final fix to tile split value on evergreen and newer v7 fix default array mode on r6xx, fix height alignment issue on evergreen v8 fix tile split value v9 add stencil tile split support, simplify dri2 for stencil with evergreen v10 Try to fix xv path regarding tiling. Adapt to libdrm API change. Try to fix case where there is no surface which means non tiled bo. v11 check for proper libdrm Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-01-10EXA/r6xx+: fix rop setting for overlapping copiesAlex Deucher
Need to use GXCopy for the src to temp copy, then the original rop for the temp to dest copy. Noticed by: Frank Huang Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-11-21ddx/evergreen: Fix endian of ALU constantsBenjamin Herrenschmidt
The constants are written directly into a buffer object shared with the card and we "forget" to swap them. This patch fixes it by doing the swap in evergreen_set_alu_consts() in-place (ie, it modifies the buffer), which should be fine with the way we use it in the ddx. This makes everything work fine on my caicos card on a G5 including some quik tests with Xv, gnome3 shell, etc... Thanks a lot to Jerome Glisse for holding my hand through debugging that (and finding the actual bug). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-10-27EXA >= R6xx / KMS: Avoid running out of CS space at inconvenient times.Michel Dänzer
Otherwise we may end up with things not properly set up at the beginning of the next CS. Fixes http://bugs.debian.org/645007 . In contrast to the Composite code for < R6xx, this isn't necessary with UMS, as the draw packet only uses constant space in the indirect buffer, and nothing else can mess with the 3D state between indirect buffers. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-05-24Revert "cayman: add scissors workaround."Alex Deucher
Needs a proper workaround for a hw bug. This reverts commit b77d374b0d11f48c33cfffdb4157c4ec4b05ea15.
2011-05-24cayman: enable all accelDave Airlie
2011-05-24cayman: add scissors workaround.Dave Airlie
wasted a lot of time getting to this.
2011-05-24cayman: first pass at exa/Xv shadersAlex Deucher
Main differences with evergreen: - 4-way rather than 5-way - END_OF_PROGRAM bit removed from CF istructions, use CF_INST_END instead. - MEGA_FETCH* fields removed from VTX commands - no more VC, all fetches go through the TC Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-24kms/cayman: stub out exa supportAlex Deucher
Just fallbacks for now. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-04radeon: add add hw DFS support for fusionDave Airlie
Fusion had a bug setting up the VM on earlier kernels so we need to work around that and only enable accel on a new enough kernel. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-20EXA/Xv: used cached bo tiling flags for accel setup on 6xx+Alex Deucher
This avoids calling into the kernel for each bo in the accel code. This is a follow on to: cc7d1fa39da40a532fcdbe6c7924ca47a879e66a Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-05EXA: Cache BO tiling flags.Michel Dänzer
Calling into the kernel every time is quite expensive, and nobody else should ever change the tiling flags. There's still more to do along the same lines for >= R6xx.
2011-03-16radeon/exa: correct function nameDave Airlie
this corrects the function name so it matches the contents. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-02r6xx+: truncate point sampled coordinatesAlex Deucher
By default the hardware rounds texcoords. However, for point sampled textures, the expected behavior is to truncate. When we have point sampled textures, set the truncate bit in the sampler. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-16kms: EXA/Xv tiling fixesAlex Deucher
- properly set tiling flags for temp surfaces - fix CB non_disp_tiling bits on evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-11kms: evergreen/ni big endian accel supportAlex Deucher
Based on 6xx/7xx patches from Cédric Cano. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-11kms/exa: UTS/DFS base alignment fixesAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-11EXA/r6xx+: properly account for height alignment in copy temp bufferAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10remove EVERGREENSetAccelState()Alex Deucher
It was a duplicate of the R600 variant. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-106xx+: switch to linear aligned rather than linear generalAlex Deucher
linear aligned is supposedly more performant, but more importantly, linear general only works on the CB without slices. The texture blocks technically don't support linear general although, I think linear general gets upgraded to linear aligned in the hw which is why it currently works. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10evergreen/NI: consolidate spi setupAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10evergreen/ni: consolidate CB state handlingAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10kms/r6xx+: clean up pitch/height alignment in EXA UTS/DFSAlex Deucher
2011-02-01kms/r6xx+: fix tiling and pageflipping harderAlex Deucher
Thanks for Michel for final fix. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=33738 for r6xx+ asics. A similar approach for pre-r6xx asics is pending. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-21evergreen: use vb_offset rather than vb_start_op for cbuf offsetAlex Deucher
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