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tv-out on atom systems is very particular about it's
dividers. force it to use the old algo.
Should fix fdo bug 27593.
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- add support for pre-avivo chips
- add support for fixed post/ref dividers
- add support for non-fractional fb dividers
By default avivo chips use the new algo and
pre-avivo chips use the old algo. Use the
"NewPLL" option to toggle between them (set to
TRUE for the new algo, FALSE for the old).
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It appears that RS4xx chips need to have the crtc
enabled when the timing is programmed.
agd5f: minor fixes/cleanup of the original patch
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noticed by Matthijs Kooijman on fdo bug 22140
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- atom dpms was unblanking for standby/suspend
- return if r600+ in radeon_crtc_modeset_ioctl()
- remove seprate standby/suspend handling in legacy
crtc dpms. we turn the outputs off, so turn the
crtcs off too.
- disable the crtcs in legacy crtc dpms
- move radeon_crtc_modeset_ioctl() calls to radeon_crtc_dpms()
so they will get called for both atom and legacy paths
Should fix bug 21321
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Allows us to hit dot clocks much closer, especially on
chips with non-27 Mhz reference clocks like most IGP chips.
This should fix most flickering and blanking problems with
non-exact dot clocks.
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This is an attempt to rationalise the code using the register info
files available to me here.
Further info is required:
r350 check for stop_req > 15 then subtract 10: what other chips need it?
get rs480 working instead of using magic.
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If set, enables the use of atombios for modesetting
on r4xx cards.
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If the crtc timing isn't setup, you might get stuck in a loop
in the BlankCRTC command table
fixes bug 16781
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Only avoid the vlines we are rendering to, instead of the entire
screen. This way we don't stall the card for longer than we
absolutely have to.
EXA calls fixed by Alex Deucher.
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- Fix up VLINE handling to trigger whenever scanout is outside the
visible area.
- Render the video as a scissored triangle as R300+ cannot render a
quad in a single pass.
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if the dest pixmap is the front buffer, stall the pipe
until the vline is outside the active area.
For EXA, pick crtc based on the larger mode area;
ideally we'd have one pixmap per crtc.
For Xv, use dst window area to determine crtc.
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Fixes sync-to-vblank hangs after mode switch with DRM vblank-rework.
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modelled after Matthias' similar rhd change
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based on Matthias' similar work in rhd
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Seems higher dotclocks prefer a higher FB div.
Someone with a lot of should try and find out where
the div sweet spots are for various dotclock ranges.
fixes bug 17125
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- makes crtc1 and crtc2 watermark setup independant.
- fixes the case where only crtc2 is active
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Patch from Jiří Paleček (see debian bug 465864) with some tweaks
by me.
- abort rather than programming bad dividers if no pll dividers can be found
- improve the pll selection algorithm
- in general, prefer lower ref dividers
I've tested this patch on a wide variety of chips (r1xx-r6xx) and clocks.
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RS400 (intel based IGP) and RS480 (AMD based IGP) have different
MC setups and need to be handled differently
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As has been done with xf86-video-intel, replace all CARD* datatypes with
uint*_t datatypes available from stdint.h.
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This reverts commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94.
Conflicts:
src/radeon.h
src/radeon_driver.c
This rework seems to have caused more trouble than it was worth.
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Setup of these registers needs more investigation.
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If you have an XPRESS chip, please test!!!
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XPRESS chips added a second set of FP control registers.
I don't have the hw to test however.
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Don't restore memmap regs on every mode switch.
Just do memmap save/restore/setup on server start and VT switch.
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Tested on my M10-based laptop.
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move save/restore routines into legacy_crtc/output
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