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This changes the vertex buffer index to be an offset, and
records the start of the vb for each operation and uses
that to set the operations up.
This still flushes after each operation to make sure we have
no regressions in non-kms/kms cases.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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we do the normalization and xforms in the vertex
shader.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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A solid or gradient mask could be used for blending
the source picture onto the destination picture.
Fixes fdo bug 24838
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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We only support per-component masks.
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Also add mysteriously missing case statements for ABGR destination formats.
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the r6xx space check code was incorrect for the DFS case, since
the dst bo was in GTT but the hardcoded cp_start function
assumed the bos were where it thought.
Ripped out assumptions and replaced with code more like other radeons.
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I'm not so sure the vb map/unmap is a good idea, I think
it pretty much locksteps the cpu/gpu, so we should really
work out if we really need to flush this often, since
mesa doesn't have to and we are just doing 3D ops.
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In particular, also catch them for >= R300.
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Apparently changing pPict->repeatType causes badness, see
http://bugs.freedesktop.org/show_bug.cgi?id=23560 .
Now we just use a normalized repeatType value derived from pPict->repeat and
pPict->repeatType everywhere.
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We can't rely on the server setting pPict->repeatType to something sensible
when pPict->repeat is FALSE, but we can do it ourselves.
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Adapted from various patches from Dave and Jerome.
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Seems problematic on all rv740 chips, so until we
can find a solution, disable them.
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Solid seem to try and handle 1bpp which really no.
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Abstract vertex buffer, preliminary work before others change
to bring cs support along IB support.
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Most of the default state setup was extraneous or duplicated
in the accel ops. There's no need to reset all the consts
everytime you reset the default state for example. This leads
to a 10x reduction in default state.
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Avoid flushing CS in the middle of (setting up state for) an operation,
properly finish/restart the operation.
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This reverts commit 11cf8a28eb46f48d101888552266921bee8b63fc.
I'll bring this back in a few minutes, I've got a big change introducing
a new cs space accounting scheme which this messes up and I think
probably conflicts with what I've done.
I promise i'll go over this and pick the bits that are still useful :)
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* Flush CS before running out of space.
* Don't flush CS every time when switching between 2D and 3D engine, but make
sure to re-initialize 2D/3D state after flushing.
Doesn't seem quite perfect yet (some rendering seems to get dropped on the floor
sometimes), but this should fix a lot of CS failures people have been seeing.
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- move to vram storage
- move swizzle logic to tex setup
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3 regs: 1 bit per bool, 32 bools per ps/vs/gs
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should now allow accel up the hw max of 8192x8192
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UTS/DFS/Xv
Doesn't seem to be reliable on AGP.
fixes bugs: 20436, 20236, several reports on ML and IRC
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As VRAM gets zeroed out over s/r, we need to reload the
shaders.
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Also fix set_bool_const()
the CF bool consts are not contiguous by shader type
There are 96 boolean constants (32 each for PS, VS, GS) and
they are ordered as follows:
ps, vs, gs ... ps, vs, gs
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use a bool const to select the tex fetch routine
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patches from Christian Koenig with some adjustments from me
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