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path: root/src/r6xx_accel.c
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2010-04-01r600/exa: further cleanup, use the object struct in the accel state.Dave Airlie
This cleans up the accel state objects as well. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-03-22r6xx EXA/Xv: track src/dst domainsAlex Deucher
Much of the code is shared, so track the src/dst domains so we make sure the uses consistent domains for each bo.
2010-03-15r6xx/r7xx: fix domain handling in accel codeAlex Deucher
Noticed by Pauli and Michel on IRC. Improves GetImage performace by a factor of ~10.
2010-02-26Use RADEON_ALIGN instead of open coding it.Matt Turner
Also fix some RADEON_ALIGN(x, 63), which would return incorrect results for odd x. Though this shouldn't happen, it's still not right. You wouldn't ever write (x + 62) & ~62 which is clearly wrong (and what it expands to). CC: Jerome Glisse <jglisse@redhat.com> CC: Alex Deucher <alexdeucher@gmail.com> CC: Dave Airlie <airlied@redhat.com> Signed-off-by: Matt Turner <mattst88@gmail.com>
2010-02-18r6xx/kms: when reseting BO force default state emissionJerome Glisse
In KMS world each cs need to fully initialize the 3D engine when we were erasing cs in IBDiscard for r6xx we weren't forcing reemission of default state. This patch force this emission. Fix : http://bugs.freedesktop.org/show_bug.cgi?id=26603 http://bugzilla.kernel.org/show_bug.cgi?id=15284
2010-02-04r600: reduce number of cache flushesAlex Deucher
We don't need to flush so often. Next step would be to move the flushing to the drm and only flush after each command buffer rather than each draw.
2010-01-18r6xx/r7xx: emit relocation for FRAG & TILE bufferJerome Glisse
FRAG & TILE buffer are unused but still they need to be associated with a valid relocation so that userspace can't try to abuse them to overwritte GART and then try to write anywhere in system memory.
2009-12-01r600: fix multi-operation in single batch support.Dave Airlie
This ports the mesa DMA buffer handling with the 3 lists, Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-27r600/accel: cleanup and merge a lot of the accel functionsDave Airlie
All of the drawing ops were the exact same modulo the vtx size, this along with the vertex buffer wrapping code could all be consolidated into a smaller set of functions. This also adds 2 VBO which we switch between, and merges a #define to enable the multiple operations in one CS under KMS mode. Multi-operation still isn't working though. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-25Revert "r600: enable multiple operations in one CS"Dave Airlie
turn this off for now, on my rv635 desktop, I started getting blanks in places in firefox and the odd bit of font corruption, need to track that down. This reverts commit 985a065518b1d33599de33f7fe082d3302db58a6.
2009-11-25r600: enable multiple operations in one CSDave Airlie
This switches on multiple ops in a single CS under KMS/DRI2. It gets for on a Pentium D 3 + rv740 from 330,000 to 500,000 with x11perf -aa10text. It also knocks a couple of seconds of gtkperf -a Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-25r600: fixup problems with EXA operation reset for multiple opsDave Airlie
To put multiple ops into one CS, you can't just discard the whole IB. This add supports for reset the CS cdw to the correct place after an op discards. Still doesn't enable the final accel bits.
2009-11-25r600: refactor code to help future acceleration speedups.Dave Airlie
This changes the vertex buffer index to be an offset, and records the start of the vb for each operation and uses that to set the operations up. This still flushes after each operation to make sure we have no regressions in non-kms/kms cases. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-24radeon/kms: drop special r600 indirect flushDave Airlie
This just merges it with the main kms cs flush
2009-10-09r600 EXA: fix up mask reg mixupAlex Deucher
2009-09-25kms/r600: add support for vline relocsAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2009-09-25radeon: fix vline handling for kmsAlex Deucher
drm crtc ids do not correspond to actual hw crtcs, as such the vline stuff was never enabled for Xv. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2009-09-25r600: space check wasn't correct.Dave Airlie
the r6xx space check code was incorrect for the DFS case, since the dst bo was in GTT but the hardcoded cp_start function assumed the bos were where it thought. Ripped out assumptions and replaced with code more like other radeons.
2009-09-10r6xx: fix EXA crash with gtkperf -aDave Airlie
unmapping was getting unbalanced.
2009-09-08r600: more alignment fixups + vb map/unmapDave Airlie
I'm not so sure the vb map/unmap is a good idea, I think it pretty much locksteps the cpu/gpu, so we should really work out if we really need to flush this often, since mesa doesn't have to and we are just doing 3D ops.
2009-08-31r6xx/r7xx: various CS fixes from DaveAlex Deucher
2009-08-26r6xx/r7xx: more WIPAlex Deucher
2009-08-25r6xx/r7xx: fix reloc for vtx bufferAlex Deucher
2009-08-25r6xx/r7xx: more cs exa wipAlex Deucher
2009-08-25r6xx/r7xx: first pass at kms accel supportAlex Deucher
Adapted from various patches from Dave and Jerome.
2009-08-25R6xx/r7xx: add begin/end batch macrosAlex Deucher
2009-08-25r6xx/r7xx: move more common state to default state setupAlex Deucher
2009-08-11radeon/r600: abstract vertex buffer for r600 & r700 hardwareJerome Glisse
Abstract vertex buffer, preliminary work before others change to bring cs support along IB support.
2009-08-04RS880: enable accelAlex Deucher
2009-07-23R6xx/R7xx: clip rendering to destination surface dimensionsAlex Deucher
2009-07-16R6xx/r7xx: reduce the amount of default state setupAlex Deucher
Most of the default state setup was extraneous or duplicated in the accel ops. There's no need to reset all the consts everytime you reset the default state for example. This leads to a 10x reduction in default state.
2009-06-28R6xx/R7xx: fix pixel centersRoland Scheidegger
Make sure we are using GL mode (centers at 0.5) rather than D3D mode (centers at 0.0). This also fixes fdo bug 21963.
2009-05-29Add RV740 (HD4770) supportAlex Deucher
Verified by ernstp on IRC
2009-03-26R6xx/R7xx: clean up bool const codeAlex Deucher
3 regs: 1 bit per bool, 32 bools per ps/vs/gs
2009-03-13R6xx/R7xx: fix up vline stuff along the lines of previous chipsAlex Deucher
Avoids an additional function call.
2009-03-02R6xx/R7xx EXA: combine composite mask/non-mask VSAlex Deucher
Also fix set_bool_const() the CF bool consts are not contiguous by shader type There are 96 boolean constants (32 each for PS, VS, GS) and they are ordered as follows: ps, vs, gs ... ps, vs, gs
2009-03-02R6xx/R7xx Xv: combine packed and planar shadersAlex Deucher
use a bool const to select the tex fetch routine
2009-03-01R6xx/R7xx: switch emit functions to macrosAlex Deucher
This improves performance due to decreased function call overhead.
2009-02-18R6xx/R7xx EXA/Xv: properly deal with running out of vertex buffer spaceAlex Deucher
As noted by mhopf, if VGT_MAX/MIN_INDX, etc. regs change, you need to re-emit CB blocks to avoid a hang. So, just set the VGT_MAX_INDX to a reasonably large value in the default state and don't touch them when drawing. When we run out of VB space, just draw the current buffer, grab a new one, and continue.
2009-02-17R6xx/R7xx EXA: switch to surface sync packetAlex Deucher
2009-02-07Xv vsync support on r6xx/r7xx cards.Pierre Ossman
2009-02-03Initial R6xx/R7xx EXA and textured video supportAlex Deucher