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Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=27957
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This adds back everything removed in c29157bbf5b0dd26857675282ab094082fbaed0d
except CB_FOG_*, CB_CLEAR_* and the VPORT transforms. Those shouldn't
be needed as we aren't using fog or viewport transforms. We probably don't
need all the state that was added back either but I can't reproduce any
problems here, so it's hard to say which parts are problematic.
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=28629
and several corruption reports on #radeon.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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No need to emit state that doesn't impact that we use for EXA/Xv.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Group ordered registers to save command buffer space.
Reduces the default and clipping state from 256 to 160 dwords.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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This cleans up the accel state objects as well.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Much of the code is shared, so track the src/dst
domains so we make sure the uses consistent domains
for each bo.
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Noticed by Pauli and Michel on IRC.
Improves GetImage performace by a factor of ~10.
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Also fix some RADEON_ALIGN(x, 63), which would return incorrect results
for odd x. Though this shouldn't happen, it's still not right. You
wouldn't ever write (x + 62) & ~62 which is clearly wrong (and what it
expands to).
CC: Jerome Glisse <jglisse@redhat.com>
CC: Alex Deucher <alexdeucher@gmail.com>
CC: Dave Airlie <airlied@redhat.com>
Signed-off-by: Matt Turner <mattst88@gmail.com>
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In KMS world each cs need to fully initialize the 3D engine
when we were erasing cs in IBDiscard for r6xx we weren't
forcing reemission of default state. This patch force this
emission. Fix :
http://bugs.freedesktop.org/show_bug.cgi?id=26603
http://bugzilla.kernel.org/show_bug.cgi?id=15284
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We don't need to flush so often. Next step
would be to move the flushing to the drm and only
flush after each command buffer rather than each
draw.
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FRAG & TILE buffer are unused but still they need
to be associated with a valid relocation so that
userspace can't try to abuse them to overwritte
GART and then try to write anywhere in system
memory.
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This ports the mesa DMA buffer handling with the 3 lists,
Signed-off-by: Dave Airlie <airlied@redhat.com>
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All of the drawing ops were the exact same modulo the vtx size,
this along with the vertex buffer wrapping code could all be consolidated
into a smaller set of functions.
This also adds 2 VBO which we switch between, and merges a #define to
enable the multiple operations in one CS under KMS mode.
Multi-operation still isn't working though.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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turn this off for now, on my rv635 desktop, I started getting blanks
in places in firefox and the odd bit of font corruption, need to
track that down.
This reverts commit 985a065518b1d33599de33f7fe082d3302db58a6.
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This switches on multiple ops in a single CS under KMS/DRI2.
It gets for on a Pentium D 3 + rv740 from 330,000 to 500,000
with x11perf -aa10text.
It also knocks a couple of seconds of gtkperf -a
Signed-off-by: Dave Airlie <airlied@redhat.com>
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To put multiple ops into one CS, you can't just discard the whole
IB. This add supports for reset the CS cdw to the correct place
after an op discards.
Still doesn't enable the final accel bits.
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This changes the vertex buffer index to be an offset, and
records the start of the vb for each operation and uses
that to set the operations up.
This still flushes after each operation to make sure we have
no regressions in non-kms/kms cases.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This just merges it with the main kms cs flush
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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drm crtc ids do not correspond to actual hw crtcs,
as such the vline stuff was never enabled for Xv.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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the r6xx space check code was incorrect for the DFS case, since
the dst bo was in GTT but the hardcoded cp_start function
assumed the bos were where it thought.
Ripped out assumptions and replaced with code more like other radeons.
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unmapping was getting unbalanced.
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I'm not so sure the vb map/unmap is a good idea, I think
it pretty much locksteps the cpu/gpu, so we should really
work out if we really need to flush this often, since
mesa doesn't have to and we are just doing 3D ops.
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Adapted from various patches from Dave and Jerome.
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Abstract vertex buffer, preliminary work before others change
to bring cs support along IB support.
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Most of the default state setup was extraneous or duplicated
in the accel ops. There's no need to reset all the consts
everytime you reset the default state for example. This leads
to a 10x reduction in default state.
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Make sure we are using GL mode (centers at 0.5) rather
than D3D mode (centers at 0.0). This also fixes fdo
bug 21963.
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Verified by ernstp on IRC
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3 regs: 1 bit per bool, 32 bools per ps/vs/gs
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Avoids an additional function call.
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Also fix set_bool_const()
the CF bool consts are not contiguous by shader type
There are 96 boolean constants (32 each for PS, VS, GS) and
they are ordered as follows:
ps, vs, gs ... ps, vs, gs
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use a bool const to select the tex fetch routine
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This improves performance due to decreased function call
overhead.
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As noted by mhopf, if VGT_MAX/MIN_INDX, etc. regs change, you need to re-emit
CB blocks to avoid a hang. So, just set the VGT_MAX_INDX to a reasonably large value
in the default state and don't touch them when drawing. When we run out of VB space,
just draw the current buffer, grab a new one, and continue.
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