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If Mesa set it to 1, the DDX would not render anything = the monitor would
basically freeze.
agd5f: update emit count as well.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Use libdrm common surface code so mesa,ddx have same idea
about tiling surface and what their pitch should be and
the alignment constraint.
v2 fix remaining issue add new option to conditionaly enable
v3 fix fbcon copy and r600 exa copy path
v4 fix non tiled path 2D tiling on GPU >= R600, set it to false
as default
v5 adapt to pixel/element size split of libdrm/radeon
v6 update to properly handle falling back to 1d tiled
v6 final fix to tile split value on evergreen and newer
v7 fix default array mode on r6xx, fix height alignment issue
on evergreen
v8 fix tile split value
v9 add stencil tile split support, simplify dri2 for stencil
with evergreen
v10 Try to fix xv path regarding tiling. Adapt to libdrm API
change. Try to fix case where there is no surface which
means non tiled bo.
v11 check for proper libdrm
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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The range passed in is in pixmap coordinates, so the CRTC offset needs to be
added to the clamping limits and subtracted from the clamped range for
pre-AVIVO display engines.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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The clamping could turn a previously non-empty range into an empty one.
Also, start == stop means the range is empty.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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On r5xx+, vline is relative to to the viewport, not
the scanlines. Based on initial patch and investigation
from Herbert Pötzl (Bertl) on IRC.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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agd5f: minor cleanups
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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We already reset vb_start_op to -1 in the
UMS/KMS ib discard functions.
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git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati
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some stray - signs
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this way we can share the vbo code with const buffers
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Based on the r6xx/r7xx code updated for evergreen.
Still causes GPU hangs in some cases. We haven't
tracked down why yet. Might be related to constant
buffer persistence.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Requires radeon drm 2.6.0 and updated mesa.
v2: - fix lockup due to not emiting DB_DEPTH_INFO
https://bugs.freedesktop.org/show_bug.cgi?id=28342
- fix drm minor version to deal with evergreen accel
v3: rebase on current ddx git
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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reduces code duplication.
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This is a precursor for r300/500 vbo support.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=27957
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This adds back everything removed in c29157bbf5b0dd26857675282ab094082fbaed0d
except CB_FOG_*, CB_CLEAR_* and the VPORT transforms. Those shouldn't
be needed as we aren't using fog or viewport transforms. We probably don't
need all the state that was added back either but I can't reproduce any
problems here, so it's hard to say which parts are problematic.
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=28629
and several corruption reports on #radeon.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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No need to emit state that doesn't impact that we use for EXA/Xv.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Group ordered registers to save command buffer space.
Reduces the default and clipping state from 256 to 160 dwords.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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This cleans up the accel state objects as well.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Much of the code is shared, so track the src/dst
domains so we make sure the uses consistent domains
for each bo.
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Noticed by Pauli and Michel on IRC.
Improves GetImage performace by a factor of ~10.
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Also fix some RADEON_ALIGN(x, 63), which would return incorrect results
for odd x. Though this shouldn't happen, it's still not right. You
wouldn't ever write (x + 62) & ~62 which is clearly wrong (and what it
expands to).
CC: Jerome Glisse <jglisse@redhat.com>
CC: Alex Deucher <alexdeucher@gmail.com>
CC: Dave Airlie <airlied@redhat.com>
Signed-off-by: Matt Turner <mattst88@gmail.com>
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In KMS world each cs need to fully initialize the 3D engine
when we were erasing cs in IBDiscard for r6xx we weren't
forcing reemission of default state. This patch force this
emission. Fix :
http://bugs.freedesktop.org/show_bug.cgi?id=26603
http://bugzilla.kernel.org/show_bug.cgi?id=15284
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We don't need to flush so often. Next step
would be to move the flushing to the drm and only
flush after each command buffer rather than each
draw.
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FRAG & TILE buffer are unused but still they need
to be associated with a valid relocation so that
userspace can't try to abuse them to overwritte
GART and then try to write anywhere in system
memory.
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This ports the mesa DMA buffer handling with the 3 lists,
Signed-off-by: Dave Airlie <airlied@redhat.com>
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All of the drawing ops were the exact same modulo the vtx size,
this along with the vertex buffer wrapping code could all be consolidated
into a smaller set of functions.
This also adds 2 VBO which we switch between, and merges a #define to
enable the multiple operations in one CS under KMS mode.
Multi-operation still isn't working though.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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turn this off for now, on my rv635 desktop, I started getting blanks
in places in firefox and the odd bit of font corruption, need to
track that down.
This reverts commit 985a065518b1d33599de33f7fe082d3302db58a6.
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This switches on multiple ops in a single CS under KMS/DRI2.
It gets for on a Pentium D 3 + rv740 from 330,000 to 500,000
with x11perf -aa10text.
It also knocks a couple of seconds of gtkperf -a
Signed-off-by: Dave Airlie <airlied@redhat.com>
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To put multiple ops into one CS, you can't just discard the whole
IB. This add supports for reset the CS cdw to the correct place
after an op discards.
Still doesn't enable the final accel bits.
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This changes the vertex buffer index to be an offset, and
records the start of the vb for each operation and uses
that to set the operations up.
This still flushes after each operation to make sure we have
no regressions in non-kms/kms cases.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This just merges it with the main kms cs flush
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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drm crtc ids do not correspond to actual hw crtcs,
as such the vline stuff was never enabled for Xv.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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the r6xx space check code was incorrect for the DFS case, since
the dst bo was in GTT but the hardcoded cp_start function
assumed the bos were where it thought.
Ripped out assumptions and replaced with code more like other radeons.
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unmapping was getting unbalanced.
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I'm not so sure the vb map/unmap is a good idea, I think
it pretty much locksteps the cpu/gpu, so we should really
work out if we really need to flush this often, since
mesa doesn't have to and we are just doing 3D ops.
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Adapted from various patches from Dave and Jerome.
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