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- move to vram storage
- move swizzle logic to tex setup
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As VRAM gets zeroed out over s/r, we need to reload the
shaders.
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If set, enables the use of atombios for modesetting
on r4xx cards.
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Also fix set_bool_const()
the CF bool consts are not contiguous by shader type
There are 96 boolean constants (32 each for PS, VS, GS) and
they are ordered as follows:
ps, vs, gs ... ps, vs, gs
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use a bool const to select the tex fetch routine
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Reduces the vertex buffer setup overhead
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git+ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati
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Otherwise it and RADEONBiggerCrtcArea show up pretty high in x11perf -aa*text
profiles.
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This reverts commit 0c4694c58f2ec152b19023626bc7ced891d9da65.
This patch just adds latency and thus isn't a real solution
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Really we need proper fencing with timestamps but this should
help in the short term.
This should help with minor corruption issues and possibly
lockups.
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This code is still experimental but we will allow users to enable it for experimental reasons
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This should fix some missing font issues in EXA without DRI cases.
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This adds support for the digital outputs on the RV730.
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Thanks to Joseph Adams for helping me sort this out.
Verified on eMac G4/1.0 with radeon 7500
Later eMacs with radeon 9200 or 9600 chips may have
different ddc setups. Need to verify.
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Only avoid the vlines we are rendering to, instead of the entire
screen. This way we don't stall the card for longer than we
absolutely have to.
EXA calls fixed by Alex Deucher.
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if the dest pixmap is the front buffer, stall the pipe
until the vline is outside the active area.
For EXA, pick crtc based on the larger mode area;
ideally we'd have one pixmap per crtc.
For Xv, use dst window area to determine crtc.
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- fixes bug 18864
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The radeon driver is storing PCI addresses in unsigned long's which
won't work well on 32-bit platforms with 64-bit physical address space
such as PowerPC 4xx. This fixes it by using unsigned long long instead.
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should fix bug 11300
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This is a setup patch for the kms/memory management code.
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Acceleration needs to be initialized before setting the mode
for initial rotation to work. Changing the order in RADEONScreenInit()
doesn't work because RADEONDRIKernelInit() hangs in the ioctl to
initialize the CP if the mode is not set prior (even if the heads
are turned off after setting the mode). The workaround is to set the
modes twice, once before accel and once after.
This needs to be looked into further.
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modelled after Matthias' similar rhd change
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based on Matthias' similar work in rhd
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- remove unused vars
- remove static exa render vars
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Seems higher dotclocks prefer a higher FB div.
Someone with a lot of should try and find out where
the div sweet spots are for various dotclock ranges.
fixes bug 17125
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They should only affect 3D and init3d() should take care of that case
noticed by libv on IRC.
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- unify the ddc and i2c code
- add gpio mask support for legacy chips
- remove the magic gpio dance for ancient monitors
(if you have an ancient monitor that ddc stops
working on let me know). This should speed up DDC
on legacy chips.
-- radeon sw gpio i2c --
4 sets of gpio registers for clk and data and corresponding bit masks
mask - locks the gpio for use by sw
get - reads the value off the gpio pad
put - sets the gpio direction to output
a - "other stuff" On legacy chips you clear them if you want
to use a gpio for i2c. In some cases they are used for the
output value when the gpio in the output state.
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Some M6 chips have a faulty MEM_SIZE register that in
some cases reports 0 on 8 MB cards. On EnterVT we check
the MEM_SIZE reg as a check to see if the card is posted or
not. Since this reg returns 0, the driver attempts to post
the card which can lead to a hang. Switch this to check if
either crtc is active as is done in the bios init code.
fixes bug 13994
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- makes crtc1 and crtc2 watermark setup independant.
- fixes the case where only crtc2 is active
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