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2012-05-24radeon: update compat-api.h for block handler + enable/disable fb.Dave Airlie
This updates the compat stuff for the latest block handler code, and the enable/disable interface. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-23compat for new server APIDave Airlie
2012-05-23ati: convert to new screen conversion APIsDave Airlie
The compat header takes care of the old server vs new server. this commit was autogenerated from util/modular/x-driver-screen-scrn-conv.sh Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-23radeon: add compat-api.hDave Airlie
2012-05-23radeon/xaa: drop scrnIndex parameter to some functionsDave Airlie
This isn't needed, and makes api changes later easier. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-02radeon: add MacModel entry for SAM440ep embedded boardAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-02-06r600-evergreen: use common surface allocator for tiling v11Jerome Glisse
Use libdrm common surface code so mesa,ddx have same idea about tiling surface and what their pitch should be and the alignment constraint. v2 fix remaining issue add new option to conditionaly enable v3 fix fbcon copy and r600 exa copy path v4 fix non tiled path 2D tiling on GPU >= R600, set it to false as default v5 adapt to pixel/element size split of libdrm/radeon v6 update to properly handle falling back to 1d tiled v6 final fix to tile split value on evergreen and newer v7 fix default array mode on r6xx, fix height alignment issue on evergreen v8 fix tile split value v9 add stencil tile split support, simplify dri2 for stencil with evergreen v10 Try to fix xv path regarding tiling. Adapt to libdrm API change. Try to fix case where there is no surface which means non tiled bo. v11 check for proper libdrm Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-01-05DPMS: Split non-modeset CRTC DPMS function.Egbert Eich
RADEONRestore() calls crtc->funcs->dpms() after most of the mode setting subsystems have been restored. This function enables the CRTCs but does more: it calls DRM pre- and post-modeset ioctls and sets up the palettes (LUTs). None of these two things are needed. Accessing the palette registers after restoring the PLLs can even lead to lockups. Thus the CRTC DPMS function is split into two parts: one that just enables /disables the CRTC and one which wraps this function and does the rest. Now the inner function can be called directly from RADEONRestore() as there is no need to go thru the RandR hooks in this function while the RandR hook uses the wrappering function so the full functionality is preserved from an RandR point of view. Signed-off-by: Egbert Eich <eich@freedesktop.org> Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
2012-01-05UMS: Fix lockups in palette save/restore on pre-AVIVO chips.Egbert Eich
The reintroduction of palette save/restore in 5efdf514 causes some pre-AVIVO chips to lock up. An investigation revealed that accessing palette registers when the associated PLL is not running is causing this. With UMS the PLL setup that is saved has been done by the BIOS typically. A similar issue was observed when VGA palette save/restore had been reinitroduced with 80eee856: http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=480312 and has been worked around for Linux without further investigation by 87e66ce7. To fix the issue we now a. introduce 'on-demand' palette saving (ie the palette is saved before it is first altered). This guarantees that the palette register are only associated when the associated CRTC is active and thus the PLLs are powered up and running. b. move palette restore before PLL restore. c. eliminate generic VGA palette save/restore which seems to be unneeded when the palette is restored natively. It is believed that this caused the behavior described in https://bugs.freedesktop.org/show_bug.cgi?id=18407#c27 Signed-off-by: Egbert Eich <eich@freedesktop.org> Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
2011-12-05radeon: r200 depth buffers are always tiledDave Airlie
When we do the allocations we need to make sure the always tiled nature is taken into account. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-08UMS: Guard references to PCITAG / pciTag with XSERVER_LIBPCIACCESS (bug #42690)Michel Dänzer
Should fix https://bugs.freedesktop.org/show_bug.cgi?id=42690 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2011-11-04DRI/DRI2: remove hard-coded limitation to 6 crtcsIlija Hadzic
DRM's hard limit to the number of CRTCs is 32. ATI DDX unnecessarily clips this limit to 6 by hard coding initial assumption for output->possible_crtcs mask to 0x7f (before it gets trimmed down to what's really possible for a given output) and by allocating only 6 entries for for cursor_bo[] array in RADEONInfoRec. Fix this and thus allow the ATI DDX to deal with as many CRTCs as the DRM allows (32), so it is ready if anything with >6 CRTCs comes out. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
2011-10-27EXA >= R6xx / KMS: Avoid running out of CS space at inconvenient times.Michel Dänzer
Otherwise we may end up with things not properly set up at the beginning of the next CS. Fixes http://bugs.debian.org/645007 . In contrast to the Composite code for < R6xx, this isn't necessary with UMS, as the draw packet only uses constant space in the indirect buffer, and nothing else can mess with the 3D state between indirect buffers. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-10-20radeon/kms: fallback to vesa if GPU is not supported by UMSJerome Glisse
For GPU not supported by UMS, test in probe so that we properly fallback to vesa. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-05-31radeon: add support for llano APUsAlex Deucher
- KMS only - Includes full EXA/Xv support Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-24cayman: first pass at exa/Xv shadersAlex Deucher
Main differences with evergreen: - 4-way rather than 5-way - END_OF_PROGRAM bit removed from CF istructions, use CF_INST_END instead. - MEGA_FETCH* fields removed from VTX commands - no more VC, all fetches go through the TC Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-04radeon: add add hw DFS support for fusionDave Airlie
Fusion had a bug setting up the VM on earlier kernels so we need to work around that and only enable accel on a new enough kernel. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-20EXA/Xv: used cached bo tiling flags for accel setup on 6xx+Alex Deucher
This avoids calling into the kernel for each bo in the accel code. This is a follow on to: cc7d1fa39da40a532fcdbe6c7924ca47a879e66a Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-05EXA: Cache BO tiling flags.Michel Dänzer
Calling into the kernel every time is quite expensive, and nobody else should ever change the tiling flags. There's still more to do along the same lines for >= R6xx.
2011-04-05DRI2: Some cleanups for the scheduling mess.Michel Dänzer
* Fix build against libdrm that doesn't define *_VBLANK_HIGH_CRTC*. * If we have more than two CRTCs but can't use DRM_VBLANK_HIGH_CRTC_MASK, don't enable scheduling in the first place rather than relying on DRM_VBLANK_SECONDARY magically doing something sensible for higher CRTCs. * Only set up client state tracking when scheduling is enabled. * Only declare pRADEONEnt when it's needed, and break long lines.
2011-04-02xf86-video-ati: (revised #2) add support for vblank on crtc > 1Ilija Hadzic
Hi Alex, Enclosed is a revised version of two patches sent on Mar 18 and Mar 22, respectively. Details summarized in these two threads: http://lists.freedesktop.org/archives/dri-devel/2011-March/009463.html http://lists.freedesktop.org/archives/dri-devel/2011-March/009582.html This patch reconciles the DDX with the change in libdrm sent to this list earlier today. Specifically, it refers to a symbol that has been renamed from DRM_CAP_HIGH_CRTC to DRM_CAP_VBLANK_HIGH_CRTC. It *supersedes* the previous patch (i.e. apply it to the master branch as it exists at the time of this writing, not as an incremental patch to the one sent previously). Regards, Ilija Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-03-16radeon/exa: correct function nameDave Airlie
this corrects the function name so it matches the contents. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-02kms: add cayman chip familyAlex Deucher
KMS only. No UMS support for cayman. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-12kms: use worst case base/pitch align if we don't have drm tiling infoAlex Deucher
To avoid CS rejection. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-106xx+: switch to linear aligned rather than linear generalAlex Deucher
linear aligned is supposedly more performant, but more importantly, linear general only works on the CB without slices. The texture blocks technically don't support linear general although, I think linear general gets upgraded to linear aligned in the hw which is why it currently works. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-10Merge branch 'kms-pflip' of ↵Alex Deucher
git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati
2011-01-06Bail on NI cards with UMSAlex Deucher
NI cards require KMS.
2011-01-06add NI family idsAlex Deucher
2010-12-03radeon/exa: fallback for non-affine transformsAlex Deucher
We need to implement a texture lookup with perspective divide for non-affine transforms. For now just fallback. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=31799 although it appears either EXA or the xserver gets this wrong too.
2010-12-01ddx/ati: Add option "SwapbuffersWait" to control vsync of DRI2 swaps.Mario Kleiner
A new optional kms driver option "SwapbuffersWait" is defined for xorg.conf, which defaults to "on". If "on", DRI2 bufferswaps will be synchronized to vsync, otherwise not. This currently only affects copy-swaps, not pageflipped swaps. It also requires a swap_interval setting of zero by the OpenGL client. Ideally, we'd provide a way for dri2 to pass the current swap interval to the ddx so we could change this dynamically. Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
2010-12-01radeon/kms: add pageflip supportAlex Deucher
requires radeon drm 2.8.0 or higher Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-22ontario: add UMS modesetting supportAlex Deucher
Accel not enabled yet. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-10-07fix the non-kms buildAlex Deucher
Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=30685
2010-10-04Merge branch 'evergreen_accel' of ↵Alex Deucher
git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati
2010-09-30radeon: fix fbLocation for >32 bit MC addressesAlex Deucher
If the fbLocation was at an address >32 bits, we'd fail. Change fbLocation to uint64_t and properly cast when needed.
2010-08-23evergreen: use vbo pool for constant buffersAlex Deucher
2010-08-23radeon: move vbo data to a separate structAlex Deucher
this way we can share the vbo code with const buffers
2010-08-20Add initial EXA and Xv support for evergreenAlex Deucher
Based on the r6xx/r7xx code updated for evergreen. Still causes GPU hangs in some cases. We haven't tracked down why yet. Might be related to constant buffer persistence. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-08-10evergreen: add support to parse firmware info for ext dp clkDave Airlie
2010-08-05r6xx/r7xx: add support for tiling with kms (v3)Alex Deucher
Requires radeon drm 2.6.0 and updated mesa. v2: - fix lockup due to not emiting DB_DEPTH_INFO https://bugs.freedesktop.org/show_bug.cgi?id=28342 - fix drm minor version to deal with evergreen accel v3: rebase on current ddx git Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-08-01radeon/r600: restructure exa + vbo to provide more sharingDave Airlie
This is a precursor for r300/500 vbo support. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-07-30r6xx/r7xx: unify composite mask and non-mask pixel shaderAlex Deucher
2010-04-21Kill per-context SAREA support.Owain G. Ainsworth
It has never been used, and since the world is changing it almost certainly never will be. Good riddance. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-21Remove remnants of the ShowCache option.Owain G. Ainsworth
The rest of it died a long time ago. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-16r1xx texvid: deal with large numbers of vertsAlex Deucher
should fix fdo bug 25884
2010-04-16radeon/kms: fix crash when using more than two headsAlex Deucher
fixes fdo bug 27692
2010-04-13radeon: add support for pll algo selectionAlex Deucher
tv-out on atom systems is very particular about it's dividers. force it to use the old algo. Should fix fdo bug 27593.
2010-04-01r600/exa: further cleanup, use the object struct in the accel state.Dave Airlie
This cleans up the accel state objects as well. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-03-22r6xx+ EXA: always use the accel_state state in DoPrepareCopyAlex Deucher
2010-03-22r6xx EXA/Xv: track src/dst domainsAlex Deucher
Much of the code is shared, so track the src/dst domains so we make sure the uses consistent domains for each bo.
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