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2018-08-29EXA: Handle ihandle == -1 in RADEONEXASharePixmapBackingMichel Dänzer
2018-07-12Replace 'foo == NULL' with '!foo'Michel Dänzer
Shorter and sweeter. :) (Ported from amdgpu commit e8e688f3852fb06b0c34ed5bce47c9493bcd1613) Acked-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-09Add struct radeon_bufferMichel Dänzer
Inspired by amdgpu, preparation for the following change. For now, this is mostly a wrapper around struct radeon_bo, no functional change intended. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-09EXA: Remove old RADEONEXACreatePixmap hookMichel Dänzer
Not used by any supported version of xserver. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-30Require xserver >= 1.13Michel Dänzer
xserver 1.13.0 was released on September 6th, 2012, almost 5 years ago. This allows cleaning up a bunch of backwards compatibility code. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2017-06-30Use pRADEONEnt->fd exclusively for the DRM file descriptorMichel Dänzer
This brings us closer to amdgpu. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-11Use reference counting for tracking KMS framebuffer lifetimesMichel Dänzer
References are held by the pixmaps corresponding to the FBs (so the same KMS FB can be reused as long as the pixmap exists) and by the CRTCs scanning out from them (so a KMS FB is only destroyed once it's not being scanned out anymore, preventing intermittent black screens and worse issues due to a CRTC turning off when it should be on). v2: * Only increase reference count in drmmode_fb_reference if it was sane before * Make drmmode_fb_reference's indentation match the rest of drmmode_display.h Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-03-17Handle tiling in radeon_set_shared_pixmap_backingDavid Heidelberger
[ Michel Dänzer: Fixups for glamor ] Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz> Signed-off-by: Axel Davy <axel.davy@ens.fr> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-12radeon: drop redundant radeon_drm.h includesAndreas Boll
Already included via radeon.h. Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
2013-07-10Always go through DFS/UTS when byte swapping is needed.Mark Kettenis
Before commit ef9bfb262db7004bef3704e5d914687e50d3fca4 and e5bd99faa3b6629a55168386d5dfa936ee4e97ae, byte swapping for the front buffer used to be done in hardware. Now that this no longer happens we need to let DFS/UTS ihandle the byte swapping. See https://bugs.freedesktop.org/show_bug.cgi?id=66663 . Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2013-03-22glamor: Initial PRIME pixmap sharing hooks.Michel Dänzer
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57200 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Christoph Haag <haagch.christoph@googlemail.com> Tested-by: linedot <linedot@xcpp.org>
2013-01-10Drop support for X servers older than 1.7.Michel Dänzer
The main purpose is to drop DRI2 compatibility code paths which are getting awkward to deal with and at this point are probably only tested lightly if at all. xserver 1.7 was released more than 3 years ago, and 1.6.2 was already required before. Mostly mechanical, there's probably potential for more cleanups. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-03radeon: add pixmap sharing hooks.Dave Airlie
This hooks into EXA and the dirty tracking to add sharing and output offload support. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-07-10Initial glamor support.Michel Dänzer
Enable at build time with --enable-glamor and runtime with Option "AccelMethod" "glamor" The most notable lack of functionality is XVideo. Use something like VDPAU for now. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-05EXA: Factor out pixmap BO allocation into a helper function.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-06-15radeon: drop radeonGetPixmapOffsetDave Airlie
no longer needed. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: move macros into radeon.hDave Airlie
Drop separate header file, there isn't many separate macros now. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: drop more wrapper macros.Dave Airlie
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: further macro cleanups.Dave Airlie
drop some more of the wrapper macros. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15drop RING_LOCALS/ACCEL_PREAMBLEDave Airlie
these were unused now. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: drop all UMS/DRI1/XAA/overlay support.Dave Airlie
This overhauls the radeon driver and removes all the old UMS-only code, it drops all the UMS, DRI1, XAA, overlay Xv, video capture, tv tuners There are probably a lot more cleanups that will fall out of this afterwards. So far this is compile/build tested. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-23ati: convert to new screen conversion APIsDave Airlie
The compat header takes care of the old server vs new server. this commit was autogenerated from util/modular/x-driver-screen-scrn-conv.sh Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-04-05r6xx-r9xx: force 1D tiling for buffer with height < 64Jerome Glisse
Due to some old kernel issue, height is 8 aligned insided the ddx For buffer with height btw 57 & 63 this lead ddx to believe it can allocate a 2D tiled surface while mesa will not align height and will assume 1D tiled leading to disagreement and rendering issue. This patch force buffer with height < 64 to be 1D tiled. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-06r600-evergreen: use common surface allocator for tiling v11Jerome Glisse
Use libdrm common surface code so mesa,ddx have same idea about tiling surface and what their pitch should be and the alignment constraint. v2 fix remaining issue add new option to conditionaly enable v3 fix fbcon copy and r600 exa copy path v4 fix non tiled path 2D tiling on GPU >= R600, set it to false as default v5 adapt to pixel/element size split of libdrm/radeon v6 update to properly handle falling back to 1d tiled v6 final fix to tile split value on evergreen and newer v7 fix default array mode on r6xx, fix height alignment issue on evergreen v8 fix tile split value v9 add stencil tile split support, simplify dri2 for stencil with evergreen v10 Try to fix xv path regarding tiling. Adapt to libdrm API change. Try to fix case where there is no surface which means non tiled bo. v11 check for proper libdrm Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2011-12-06radeon: refine always tiled depth checkDave Airlie
So it appears the M7 family always tiles its depth buffer also. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-05radeon: r200 depth buffers are always tiledDave Airlie
When we do the allocations we need to make sure the always tiled nature is taken into account. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-20EXA/Xv: used cached bo tiling flags for accel setup on 6xx+Alex Deucher
This avoids calling into the kernel for each bo in the accel code. This is a follow on to: cc7d1fa39da40a532fcdbe6c7924ca47a879e66a Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-05EXA: Cache BO tiling flags.Michel Dänzer
Calling into the kernel every time is quite expensive, and nobody else should ever change the tiling flags. There's still more to do along the same lines for >= R6xx.
2011-03-16radeon/exa: correct function nameDave Airlie
this corrects the function name so it matches the contents. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-16radeon/exa: fix scaling checkDave Airlie
This caused a regression in firefox, as these numbers are xFixed values hence 1 is actually 65536. Should fix: https://bugzilla.redhat.com/show_bug.cgi?id=685084 Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-15radeon: exa shaders don't handle scaling either.Dave Airlie
rendercheck tsrccoords test fails. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-01kms/pre-6xx: fix pageflipping with tilingAlex Deucher
Use UTS/DFS to tile/untile as appropriate for sw access on pre-6xx. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=33738 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-10Merge branch 'kms-pflip' of ↵Alex Deucher
git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati
2010-12-03radeon/exa: fallback for non-affine transformsAlex Deucher
We need to implement a texture lookup with perspective divide for non-affine transforms. For now just fallback. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=31799 although it appears either EXA or the xserver gets this wrong too.
2010-12-01radeon/kms: allow tiled front buffer on 6xx/7xxAlex Deucher
Use UTS/DFS to tile/untile as appropriate for sw access. Also enables pageflipping with tiling enabled.
2010-11-17radeon/kms: fix buffer base alignment for tilingAlex Deucher
On r6xx+, 2D tiling can require larger than 4k base alignment.
2010-10-27drm/radeon: unify fb bo alignment harderAlex Deucher
More duplicated paths discoved...
2010-10-27kms/radeon: unify fb bo alignment handlingAlex Deucher
Previously there were 3 different paths with what should have had duplicated code: - EXACreatePixmap2 - Initial front buffer creation - Randr resize This patch attempts to unify the alignment across all 3. This may fix tiling issues in some cases and should make buffer pitches match for pageflipping.
2010-10-19r600: for 2d tiles we need to align to channels no banks.Dave Airlie
2010-09-20RADEONPrepareAccess_CS: fallback to DFS when pixmap is in VRAMKarl Tomlinson
This avoids costly CPU VRAM reads and lets EXA manage a system memory cache of the portions of pixmaps needed for unaccelerated operations. https://bugs.freedesktop.org/show_bug.cgi?id=27139
2010-09-20FinishAccess_CS: set bo_mapped to FALSE on unmapKarl Tomlinson
This is actually only necessary when PrepareAccess may behave differently on different calls with the same pixmap, which currently doesn't happen. However resetting bo_mapped is necessary to let PrepareAccess (with mixed pixmaps) choose to fail based on whether the pixmap is in VRAM (to avoid CPU reads).
2010-08-05r6xx/r7xx: add support for tiling with kms (v3)Alex Deucher
Requires radeon drm 2.6.0 and updated mesa. v2: - fix lockup due to not emiting DB_DEPTH_INFO https://bugs.freedesktop.org/show_bug.cgi?id=28342 - fix drm minor version to deal with evergreen accel v3: rebase on current ddx git Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-08-01radeon/r600: restructure exa + vbo to provide more sharingDave Airlie
This is a precursor for r300/500 vbo support. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-06-21Convert x(c)alloc/xfree to m/calloc/free.Michel Dänzer
Fixes deprecation warnings with xserver master and should also work with older xservers.
2010-05-18rs740: follow macro-switch tooMarek Olšák
Signed-off-by: Marek Olšák <maraeo@gmail.com>
2010-05-04r3xx-r5xx: fix texturing with small macrotiled pixmapsMarek Olšák
Pixmaps smaller than a macrotile cannot be used as textures because hardware automatically switches to macro-linear and therefore sampled pixels are messed up. This behavior is known as MACRO_SWITCH. The only sane workaround seems to be not using macrotiling for small pixmaps. The function RADEONMacroSwitch has been ported from r300g and implements MACRO_SWITCH the same way it's implemented in hardware. It's been well tested in r300g. This commit also fixes blit-based framebuffer reads, which are used for tiled surfaces in r300g, when ColorTiling is enabled. Signed-off-by: Marek Olšák <maraeo@gmail.com>
2010-02-26Use RADEON_ALIGN instead of open coding it.Matt Turner
Also fix some RADEON_ALIGN(x, 63), which would return incorrect results for odd x. Though this shouldn't happen, it's still not right. You wouldn't ever write (x + 62) & ~62 which is clearly wrong (and what it expands to). CC: Jerome Glisse <jglisse@redhat.com> CC: Alex Deucher <alexdeucher@gmail.com> CC: Dave Airlie <airlied@redhat.com> Signed-off-by: Matt Turner <mattst88@gmail.com>
2010-02-26Use/define RADEON_GPU_PAGE_SIZE instead of sprinkling 4096 everywhere.Matt Turner
Also, define RADEON_BUFFER_ALIGN in terms of it, and replace some RADEON_ALIGN(x, RADEON_BUFFER_ALIGN) with RADEON_ALIGN(x, RADEON_GPU_PAGE_SIZE) since this is really what was intended. CC: Jerome Glisse <jglisse@redhat.com> CC: Alex Deucher <alexdeucher@gmail.com> CC: Dave Airlie <airlied@redhat.com> Signed-off-by: Matt Turner <mattst88@gmail.com>
2010-02-12radeon: consolidate crtc selector for vline waitAlex Deucher
Use the Xv version as it takes into account the area covered by the op rather than just picking the largest crtc area.
2009-12-21radeon: use new libdrm apiDave Airlie
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