Age | Commit message (Collapse) | Author |
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Shorter and sweeter. :)
(Ported from amdgpu commit e8e688f3852fb06b0c34ed5bce47c9493bcd1613)
Acked-by: Alex Deucher <alexander.deucher@amd.com>
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Inspired by amdgpu, preparation for the following change. For now, this
is mostly a wrapper around struct radeon_bo, no functional change
intended.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Not used by any supported version of xserver.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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xserver 1.13.0 was released on September 6th, 2012, almost 5 years ago.
This allows cleaning up a bunch of backwards compatibility code.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
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If we don't, we may hit a buffer that crosses the
visible vram boundary resulting in a sigbus when the
CPU accesses the buffer beyond the PCI aperture.
This will introduce an extra copy in certain cases.
This is based on Michel's patch from bug 44099 updated
for all asic families.
Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=44099
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Signed-off-by: Samuel Li <samuel.li@amd.com>
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The main purpose is to drop DRI2 compatibility code paths which are getting
awkward to deal with and at this point are probably only tested lightly if at
all. xserver 1.7 was released more than 3 years ago, and 1.6.2 was already
required before.
Mostly mechanical, there's probably potential for more cleanups.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
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This patch adds an option called consider_disabled to
radeon_pick_best_crtc function. If this option is set
and searching for best-fit CRTC yields nothing, the search
will be widened to include CRTCs in DPMS "off" state.
The new option is not used yet; it will be in the patches
to follow.
v2: Do not look at the CRTC mode, we only care about its box.
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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This hooks into EXA and the dirty tracking to add sharing and output
offload support.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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this just adds the interface and shared support to the pixmap.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This helps make a few more things static and the driver generally
smaller.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Dave Airlie <airlied@redhat.com>
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drop some more of the wrapper macros.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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These are no longer used outside this area.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Drop all the CP vs MMIO macros that name functions.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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these were unused now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This overhauls the radeon driver and removes all the old UMS-only code,
it drops all the UMS, DRI1, XAA, overlay Xv, video capture, tv tuners
There are probably a lot more cleanups that will fall out of this afterwards.
So far this is compile/build tested.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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The compat header takes care of the old server vs new server.
this commit was autogenerated from util/modular/x-driver-screen-scrn-conv.sh
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Otherwise it's basically luck what the 2D state ends up being at the beginning
of the next CS.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
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Calling into the kernel every time is quite expensive, and nobody else should
ever change the tiling flags.
There's still more to do along the same lines for >= R6xx.
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Use UTS/DFS to tile/untile as appropriate for sw access on
pre-6xx.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=33738
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Turns on the big-endian paths even for little-endian systems, and adds
similar paths to the r6xx/r7xx functions.
This makes UTS and DFS reliable, which will let PrepareAccess (with
mixed pixmaps) choose to fail based on whether the pixmap is in VRAM
(to avoid CPU reads).
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On big endian systems, PrepareAccess will fail when byte-swapping is
required so UploadToScreen and DownloadFromScreen cannot rely on
fallback to PrepareAccess.
When scratch BO space allocation fails, this patch merely adds simple
fallback to direct CPU access without any GPU blit. This sometimes
requires a CS flush even in UploadToScreen.
(No allocation retry after a flush is added here.)
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If unflushed CS operations write to the pixmap BO, then these need to be
flushed before mapping the BO for read. This currently only affects big
endian systems and only when the operation writes to the GTT domain.
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radeon_bo_is_busy() may return without setting the domain out-parameter.
If this happens, then download via a scratch GTT BO to avoid CPU VRAM read.
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Fixes deprecation warnings with xserver master and should also work with older
xservers.
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Also fix some RADEON_ALIGN(x, 63), which would return incorrect results
for odd x. Though this shouldn't happen, it's still not right. You
wouldn't ever write (x + 62) & ~62 which is clearly wrong (and what it
expands to).
CC: Jerome Glisse <jglisse@redhat.com>
CC: Alex Deucher <alexdeucher@gmail.com>
CC: Dave Airlie <airlied@redhat.com>
Signed-off-by: Matt Turner <mattst88@gmail.com>
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Also, define RADEON_BUFFER_ALIGN in terms of it, and replace some
RADEON_ALIGN(x, RADEON_BUFFER_ALIGN) with RADEON_ALIGN(x,
RADEON_GPU_PAGE_SIZE) since this is really what was intended.
CC: Jerome Glisse <jglisse@redhat.com>
CC: Alex Deucher <alexdeucher@gmail.com>
CC: Dave Airlie <airlied@redhat.com>
Signed-off-by: Matt Turner <mattst88@gmail.com>
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The wrong order prevented tearing avoidance from working with EXA/DRI2.
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Use the Xv version as it takes into account the area
covered by the op rather than just picking the largest
crtc area.
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This reverts commit b6ac42cce2156880ac18b32e15acbff40b2f53e9.
This patch is very broken.
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Signed-off-by: Tomáš Chvátal <scarabeus@gentoo.org>
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Requires at least xserver 1.7 to work properly.
Also make sure the front buffer is and stays tiled if colour tiling is enabled.
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libdrm_radeon always takes care of this implicitly now.
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Direct CPU writes should be at least as fast in that case.
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* Drop superfluous RADEONDownloadFromScreenGTT function, EXA does the same
thing when we return FALSE.
* Take unflushed operations into account for determining which GEM domain the
pixmap BO will end up in.
* Only use a blit if it ends up in VRAM.
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This uses the new libdrm busy interface, once I had this in place
I added a error if this happened and it does on my desktop here,
so may as well add the optimisation that used to be in my old KMS tree.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This requires an X server from git with createpixmap2 support fixed up in it.
On 1.6 and previous it won't do any tiling, if you are running git server
please upgrade to latest git.
Option "AllowColorTiling" "true" to enable and do some testing
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Also remove a superfluous assignment.
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Check we can handle the bpp, and remove superfluous flush.
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Fixups by Michel Dänzer: Doesn't seem to be a win in terms of raw numbers, but
should allow more pipelining and avoiding BO memory waste for small glyph
pixmaps.
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What we want to do is add userspace object support to radeon
kernel modesetting. Also this DFS is dumb and might endup doing
blit from GTT to GTT.
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Only compile tested.
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compile tested only.
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