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Please test if you have an RS600
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should fix bug 19984
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This fixes some VT switch issues on some chips
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Call EnableYUV to set the transform and enable/disable it.
should also fix green tint with tv connected at boot issues.
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- Fix up VLINE handling to trigger whenever scanout is outside the
visible area.
- Render the video as a scissored triangle as R300+ cannot render a
quad in a single pass.
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if the dest pixmap is the front buffer, stall the pipe
until the vline is outside the active area.
For EXA, pick crtc based on the larger mode area;
ideally we'd have one pixmap per crtc.
For Xv, use dst window area to determine crtc.
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work yet...
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- r1xx - switch from tri fan to rect list
- r2xx/r3xx/r4xx/r5xx - switch from tri fan to quad list
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- support for LB allocation
- MC priority bumps for display1/2 on RV515 variants and RS690
If you are having display underflow problems (flickering on sides of
screen in high res modes, etc.) on RV515 or RS690 boards, try setting:
Option "DisplayPriority" "HIGH" in your config.
- still no support for full display watermark programming yet
Something similar might be useful in rhd as well.
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- makes crtc1 and crtc2 watermark setup independant.
- fixes the case where only crtc2 is active
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This patch fixes the console switch for me on R5xx.
There are two aspects to it:
- Fix the ordering of avivo_restore() to better match what's
happening in the driver & ATOM, properly locking/unlocking and
only enabling the CRTCs after everything has been properly
programmed.
- Don't ASIC_INIT if the card has any CRTC enabled. This is the
best I came up with for avoiding spurrious ASIC_INIT on cards that
-are- POSTed but don't have the BIOS coming from c0000 on x86. The
problem with spurrious ASIC_INIT is that we do it before we do
RADEONSave(), so that screws up the console switch.
Note that I think we also should save/restore the palette, I don't think
we do. right now, it's a minor issue for me because I fixed offb to be
able to set it on AVIVO's but it might still have to be done in the long
run.
Tested with a VGA analog setup on DACA and a DVI setup on TMDS 0. I
haven't tested any other combo but that should get us going.
Cheers,
Ben.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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adds pci ids and one register from AMD code
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This should help to avoid 2d & 3d engine to step on each
other dma transaction.
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According to the hw guys, you should use DSTCACHE_CTLSTAT to
flush the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT.
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Is there any reason to still do this in the ddx?
Maybe real old drms?
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this should fix bugs 16115, 16035
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ATI provides the following algorithm to calculate the RMX scaling ratios
in its programming specs:
when RMX_AUTO_RATIO_HORZ_INC set to 1,Horizontal auto ratio result trucated,
and then incremented by 1.
Horz_Ratio = ( ((Active display width in characters (including overscan) + 1)
/ (Panel width in characters)) x 4096 + 1 )
else
Horz_Ratio = ( ((Active display width in characters (including overscan))
/ (Panel width in characters)) x 4096 + 1 )
when RMX_AUTO_RATIO_VERT_INC set to 1, Vertical auto ratio result trucated,
and then incremented by 1.
Vert_Ration = ( ((Active display width in characters (including overscan) + 1)
/ (Panel width in characters)) x 4096 + 1)
else
Vert_Ration = ( ((Active display width in characters (including overscan))
/ (Panel width in characters)) x 4096 + 1)
This patch implements this behavor. Additionally it avoids the use of floats.
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As has been done with xf86-video-intel, replace all CARD* datatypes with
uint*_t datatypes available from stdint.h.
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this should fix occasional corruption seen when updating
the cursor.
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Also add more bit defs to wait_until register
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- get pipe config based on GB_PIPE_SELECT where applicable
(adapted from a similar patch from Dave)
- only flush the dst cache after submitting vertices, freeing
the cache lines stalls the pipe
- no need to wait for 3D idle after submitting vertices
- fix PURGE_CACHE() and PURGE_ZCACHE() for r3xx+
- fix depth 16 with EXA composite
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Use the border color when possible, otherwise fall back to software.
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If you have an XPRESS chip, please test!!!
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XPRESS chips added a second set of FP control registers.
I don't have the hw to test however.
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still not working.
- swizzle US output for BGR formats
- no need to write to temps in ALU ops,
write to output only
- flush the PVS before updating
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This should fix the color banding some people have noticed.
Also save/restore DDIA regs on RS6xx
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This should fix the checkerboard issues on r300/r350 cards.
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pointed out by plaes on irc
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Just an example of how to setup and run the r500 3D engine for rotation.
this rotates for me but I get some strange clipping on the bottom of my screen
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