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Should fix Masta-G's issue reported on IRC.
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When using a mask, set explicit cache partitions for
each texture. Gives 1% performance improvement in
x11perf with anti-aliased text.
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This reverts commit f8c7d6a6162196a743f6885ecaf63ba50de1722a.
This is apparently still needed for some setups, however, I can't
reproduce this locally anymore.
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This fixes corruption for some users
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Fixes an M26 hang reported by tormod on IRC
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Force lower power mode and switch to a lower mode
when idle.
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Dyanmically switch between power states. Switch to a low
power state when the system is idle (DPMS off).
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1 lane seems to cause occasional corruption when
blitting to/from gart memory.
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Force the chip to a low power mode at the expense
of performance.
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- replaces DynamicClocks Option as the name was misleading
- unified interface for atom and com based bioses
- fix up clock gating code for newer r3xx asics
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This is an attempt to rationalise the code using the register info
files available to me here.
Further info is required:
r350 check for stop_req > 15 then subtract 10: what other chips need it?
get rs480 working instead of using magic.
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IIRC, the old randr code used to use this to use for front buffer sizing,
but it has since been changed.
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Fixes garbage being visible shortly on server startup or when VT switching back
to X.
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- remove cases that aren't possible (e.g., no TMDSA on DCE3 cards)
- condense duplicate cases
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disable the dig transmitter and encoder before setup and enable
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Should fix bug 21050
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Patch from Eduard Fuchs with some cleanup from me.
Tested at 32 bpp on MPC8641HPCN board (PowerPC) with
HD2400 PCIe card
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fixes 10fbbac4bed59e12ad794ac873dd415d9ee4e340
fixes bugs 20796 and 20979
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fixes f061308e7abcf93d1612681b935387fee23e0a24
fixes bugs 20796 and 20979
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should fix bug 13872
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fixes bug 20796
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Noticed by sroland on IRC.
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- move to vram storage
- move swizzle logic to tex setup
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3 regs: 1 bit per bool, 32 bools per ps/vs/gs
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size needs to be calculated after dstPitch adjustments, got already fixed
for earlier than R600 chips by planar textured yuv patches, clean this up.
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uses 3 textures for planar yuv and does yuv->rgb conversion in the shader.
Similar to r300 code, but might have precision issues - hardware alu should
have enough precision but hardware consts are only 8bit and we'd want
at least 11.
This also enables textured video on rv250 (and also supports packed yuv
on that chip by using basically the same shader with packed data).
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uses 3 textures for planar yuv and does yuv->rgb conversion in the shader.
small performance advantage, but manual texture cache setting is necessary
otherwise it may be measurably slower (but probably not relevant) in some
cases.
Unlike some other drivers, using MADs instead of DP3s, since this requires
less instructions due to no MOVs are required, the end result is the same
though the constants need to be different.
Use of this is user settable for now (XV_HWPLANAR attrib).
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This fixes some oddities observed when the video is only partly visible.
Instead of recalculating the geometry of the video, always use the same.
Also fixes a assignment present twice, and another issue (bring in line with
what the overlay code does).
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should fix bug 20814
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DVI seems to have issues with low dotclocks, so
use the scaler instead.
Fixes bug 20754
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