Age | Commit message (Collapse) | Author |
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This requires a drm > 1.26 to work
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Cosmetic.
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Factor out to seperate function.
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Move LCD block from atimode.c to atimach64.c .
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respect that all source planar yuv planes are already dword aligned.
Some attempts to fix up odd widths and odd heights (which are a bit strange
for 4:2:0 formats). They still don't quite work 100% correctly (at the borders)
but neither do they with packed yuv formats.
While here, fix totally broken packed UYVY format by inserting missing break...
Both bugs reported by Felipe Contreras.
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These regs are more useful than just multimedia
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This option allows you to disable the DRI per card. It also
removes the "RN50Force3D" option as it is now covered by this
option. RN50 users should set this to TRUE if they want to force
the DRI on.
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Match ATILock - ATIUnlock.
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Move {Initialize,Close}XVideo from atixv.c to atimach64xv.c .
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Merge ATIXVInitializeAdaptor() in ATIMach64XVInitialiseAdaptor().
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Merge ATIInitializeAcceleration() in ATIMach64AccelInit().
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Move ATIResizeOffscreenLinear() from atiaccel.c to atimach64xv.c and make it
static. It is only used by XV memory management functions.
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- we require a PCI device (pVideo != NULL)
- map the VGA framebuffer with xf86MapDomainMemory()
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Fixes a bug where shadowfb would not be enabled by default in the non-accel
case because pATI->PCIInfo is now set after ATIProcessOptions() is called.
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Allow user to force the DRI on for RN50 chips.
3D is not guaranteed to work on these chips,
however in some cases it does.
fixes bug 9802.
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This will be handled with an option somehow.
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From README.ati:
Clocks for supported programmable clock generators:
The driver currently supports all programmable clock generators known
to exist on Mach64 adapters.
Clocks for unsupported programmable clock generators:
This case is unlikely to occur, but is documented for the sake of
completeness.
Thus:
- check for (pATI->ProgrammableClock > ATI_CLOCK_FIXED) &&
(pATI->ProgrammableClock < ATI_CLOCK_MAX)
- drop "probe_clocks" option
- pATIHW->ClockUnmap is no longer used
- pATIHW->ClockMap is only used with NewHW.crtc which is always ATI_CRTC_MACH64
and has the identity map, so drop it
- (pATI->ProgrammableClock != ATI_CLOCK_INTERNAL) => (pATI->depth <= 8)
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- (pATI->BankInfo.BankSize = 0) in all cases, cull pATI->BankInfo
- only keep the minimal pATIHW.SetBank interface for save/restore
- clean ATISwap() a little, (NewHW.crtc != ATI_CRTC_VGA)
- (UseSmallApertures == TRUE) <=> pATI->VGAAdapter
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- drop (pATI->OptionLinear == FALSE)
- AcceleratorVideoRAM is always set, i.e. VGAVideoRAM is not used
- pATI->LinearBase is always set
- xf86LinearVidMem() is now checked in atipreinit() for both CPIO and MMIO
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- cull (pATI->NewHW.crtc != ATI_CRTC_MACH64).
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- cull (pATI->Adapter != ATI_ADAPTER_MACH64)
- treat pATI->VGAAdapter as Bool
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- Chip < ATI_CHIP_88800GXC
- Chipset != ATI_CHIPSET_ATI
- Adapter != ATI_ADAPTER_MACH64
- depth < 8
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- Chip < ATI_CHIP_88800GXC
- Chipset != ATI_CHIPSET_ATI
- Adapter != ATI_ADAPTER_MACH64
- depth < 8
atimode.c only:
- NewHW.crtc != ATI_CRTC_MACH64
This allows to drop VGACalculate(), VGAWonderCalculate() cruft early.
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- ChipHasSUBSYS_CNTL
- Coprocessor
- SharedAccelerator
- SharedVGA <=> (VGAAdapter != ATI_ADAPTER_NONE)
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This was not set anyway, because configure.ac would compute ATIMISC_NON_PCI and
then test ATI_AVOID_NON_PCI to set AVOID_NON_PCI...
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This is mainly due to the cards having a different resource 1.
Fixes 6796
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My 8500 in i845 doesn't work with fastwrites even setup by the firmware.
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This might fix bug 9371
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Since the reorganization of the mode setting code, the mode registers relying
on state already set (by bios) were not read, thus clearing out all bits the
driver does not touch. At the very least, this could lead to completely
nonfunctional to misbehaving dvi output (see bug 9495). Fix this by using the
SavedReg values, which also makes it more obvious that those are bits which
were not set by the driver previously, but come from register readback.
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Also round up to the maximum width and height, as that's what EXA compares.
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Based on the assumption that firmware should have set up the card and host
bridge appropriately for these settings, this may actually be safer, at least
for the transfer rate; leaving fast writes enabled is hopefully safe as well,
it certainly is on my sytem.
See https://bugs.freedesktop.org/show_bug.cgi?id=9284 .
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This reverts commit 48ff33a1770f3684cd50184db8f1944a456d9974.
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It is not necessary to always emit a OUTPLL/INPLL pair when we display
a video frame. On some chips there are erratas for which the workarounds
cause a 10ms delay by those calls. This is related to #5876 though those
affected may suffer from other slowness issues too.
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This unclutters RADEONPreInit() somewhat, but more importantly moves comparison
against info->ChipFamily after that's initialized.
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Instead of calling the DRM CP idle ioctl, just emit the cache flush commands
into the CP stream.
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