From dd6a966e862b774a8e8b9e1a085309219673efad Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 22 Apr 2007 11:36:00 +1000 Subject: radeon: add support for DDC on some laptop chipsets I noticed fglrx has DDC for the panel in the rs480 laptop, however radeon didn't pick it up, so I valgrinded fglrx and spotted 0x1a0/0x1a4 accesses I actually noticed this before from the BIOS but never figured it out. So now I get DDC from the LCD on this laptop. --- src/radeon_bios.c | 5 ++++- src/radeon_display.c | 44 +++++++++++++++++++++++++++++++------------- src/radeon_probe.h | 3 ++- src/radeon_reg.h | 2 ++ 4 files changed, 39 insertions(+), 15 deletions(-) diff --git a/src/radeon_bios.c b/src/radeon_bios.c index 1d4c9bbb..dd3d0a7a 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c @@ -181,6 +181,9 @@ Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) case RADEON_GPIO_CRT2_DDC: pRADEONEnt->PortInfo[crtc]->DDCType = DDC_CRT2; break; + case RADEON_LCD_GPIO_MASK: + pRADEONEnt->PortInfo[crtc]->DDCType = DDC_LCD; + break; default: pRADEONEnt->PortInfo[crtc]->DDCType = DDC_NONE_DETECTED; break; @@ -290,7 +293,7 @@ Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) if ((tmp0 = RADEON_BIOS16(tmp + 0x15))) { if ((tmp1 = RADEON_BIOS8(tmp0+2) & 0x07)) { pRADEONEnt->PortInfo[0]->DDCType = tmp1; - if (pRADEONEnt->PortInfo[0]->DDCType > DDC_CRT2) { + if (pRADEONEnt->PortInfo[0]->DDCType > DDC_LCD) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDCType %d found\n", pRADEONEnt->PortInfo[0]->DDCType); diff --git a/src/radeon_display.c b/src/radeon_display.c index 57e752e3..f3b86e6e 100644 --- a/src/radeon_display.c +++ b/src/radeon_display.c @@ -75,12 +75,13 @@ const char *TMDSTypeName[3] = { "External" }; -const char *DDCTypeName[5] = { +const char *DDCTypeName[6] = { "NONE", "MONID", "DVI_DDC", "VGA_DDC", - "CRT2_DDC" + "CRT2_DDC", + "LCD_DDC" }; const char *DACTypeName[3] = { @@ -166,10 +167,16 @@ static void RADEONI2CGetBits(I2CBusPtr b, int *Clock, int *data) unsigned char *RADEONMMIO = info->MMIO; /* Get the result */ - val = INREG(info->DDCReg); - *Clock = (val & RADEON_GPIO_Y_1) != 0; - *data = (val & RADEON_GPIO_Y_0) != 0; + if (info->DDCReg == RADEON_LCD_GPIO_MASK) { + val = INREG(info->DDCReg+4); + *Clock = (val & (1<<13)) != 0; + *data = (val & (1<<12)) != 0; + } else { + val = INREG(info->DDCReg); + *Clock = (val & RADEON_GPIO_Y_1) != 0; + *data = (val & RADEON_GPIO_Y_0) != 0; + } } static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) @@ -179,11 +186,17 @@ static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) unsigned long val; unsigned char *RADEONMMIO = info->MMIO; - val = INREG(info->DDCReg) & (CARD32)~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1); - val |= (Clock ? 0:RADEON_GPIO_EN_1); - val |= (data ? 0:RADEON_GPIO_EN_0); - OUTREG(info->DDCReg, val); - + if (info->DDCReg == RADEON_LCD_GPIO_MASK) { + val = INREG(info->DDCReg) & (CARD32)~((1<<12) | (1<<13)); + val |= (Clock ? 0:(1<<13)); + val |= (data ? 0:(1<<12)); + OUTREG(info->DDCReg, val); + } else { + val = INREG(info->DDCReg) & (CARD32)~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1); + val |= (Clock ? 0:RADEON_GPIO_EN_1); + val |= (data ? 0:RADEON_GPIO_EN_0); + OUTREG(info->DDCReg, val); + } /* read back to improve reliability on some cards. */ val = INREG(info->DDCReg); } @@ -562,13 +575,16 @@ static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCT case DDC_CRT2: info->DDCReg = RADEON_GPIO_CRT2_DDC; break; + case DDC_LCD: + info->DDCReg = RADEON_LCD_GPIO_MASK; + break; default: info->DDCReg = DDCReg; return MT_NONE; } /* Read and output monitor info using DDC2 over I2C bus */ - if (info->pI2CBus && info->ddc2) { + if (info->pI2CBus && info->ddc2 && (info->DDCReg != RADEON_LCD_GPIO_MASK)) { OUTREG(info->DDCReg, INREG(info->DDCReg) & (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); @@ -620,15 +636,17 @@ static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCT OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_1); OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_0); usleep(15000); - if(*MonInfo) break; + if(*MonInfo) break; } + } else if (info->pI2CBus && info->ddc2 && info->DDCReg == RADEON_LCD_GPIO_MASK) { + *MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, info->pI2CBus); } else { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n"); MonType = MT_NONE; } OUTREG(info->DDCReg, INREG(info->DDCReg) & - ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); + ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); if (*MonInfo) { if ((*MonInfo)->rawData[0x14] & 0x80) { diff --git a/src/radeon_probe.h b/src/radeon_probe.h index f4465163..dc30e2e9 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -48,7 +48,8 @@ typedef enum DDC_MONID, DDC_DVI, DDC_VGA, - DDC_CRT2 + DDC_CRT2, + DDC_LCD, } RADEONDDCType; typedef enum diff --git a/src/radeon_reg.h b/src/radeon_reg.h index b50fcf0a..0d5e5863 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -907,6 +907,8 @@ # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13) # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) +#define RADEON_LCD_GPIO_MASK 0x01a0 +#define RADEON_LCD_GPIO_Y_REG 0x01a4 #define RADEON_MDGPIO_A_REG 0x01ac #define RADEON_MDGPIO_EN_REG 0x01b0 #define RADEON_MDGPIO_MASK 0x0198 -- cgit v1.2.3 From 764cb73e8dec4040cdd418d249fc504399fca3ee Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sun, 20 May 2007 17:26:26 -0400 Subject: Fix regular/"xinerama"/zaphod dualhead mode - logic in RADEONUnblank() was wrong - Calling RADEONSetupConnectors() on second instance screwed up the port info - still seem to be HW cursor issues with zaphod mode --- src/radeon_display.c | 7 +++++-- src/radeon_driver.c | 4 +++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/radeon_display.c b/src/radeon_display.c index f3b86e6e..fb345a9e 100644 --- a/src/radeon_display.c +++ b/src/radeon_display.c @@ -2135,7 +2135,9 @@ void RADEONUnblank(ScrnInfoPtr pScrn) RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); RADEONConnector *pPort; - if (!pRADEONEnt->HasSecondary || (info->IsSwitching && !info->IsSecondary)) { + if (!pRADEONEnt->HasSecondary || + (pRADEONEnt->HasSecondary && !info->IsSwitching) || + (info->IsSwitching && (!info->IsSecondary))) { pPort = RADEONGetCrtcConnector(pScrn, 1); if (pPort) RADEONUnblankSet(pScrn, pPort); @@ -2158,7 +2160,8 @@ void RADEONUnblank(ScrnInfoPtr pScrn) } } - if (info->IsSwitching && info->IsSecondary) { + if ((pRADEONEnt->HasSecondary && !info->IsSwitching) || + (info->IsSwitching && info->IsSecondary)) { pPort = RADEONGetCrtcConnector(pScrn, 2); if (pPort) RADEONUnblankSet(pScrn, pPort); diff --git a/src/radeon_driver.c b/src/radeon_driver.c index b9cce22e..933265f5 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -2971,7 +2971,9 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10 RADEONGetBIOSInfo(pScrn, pInt10); - RADEONSetupConnectors(pScrn); + if (!info->IsSecondary) { + RADEONSetupConnectors(pScrn); + } RADEONMapControllers(pScrn); RADEONGetClockInfo(pScrn); -- cgit v1.2.3 From 09bfc8ed000f95ede5b73f2bad69edc1a4d9bac6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sun, 20 May 2007 18:06:22 -0400 Subject: update to 6.6.192 for rc release --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index ddfa7c8e..8b29d8d5 100644 --- a/configure.ac +++ b/configure.ac @@ -22,7 +22,7 @@ AC_PREREQ(2.57) AC_INIT([xf86-video-ati], - 6.6.191, + 6.6.192, [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], xf86-video-ati) -- cgit v1.2.3 From 137e3fc1899078af0f72303ab0a4e6cf35804a7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Mon, 21 May 2007 10:25:48 +0200 Subject: radeon: Suppress debugging output by default. It can be enabled at runtime by increasing the log verbosity level. Also change the prefix from (**) to (II) to make grepping the log file for defaults overridden by xorg.conf more useful again. Turn some MC related debugging output into normal informational output as it's useful for recognizing corner cases that can cause stability issues. --- src/radeon.h | 11 +- src/radeon_accel.c | 38 +++--- src/radeon_commonfuncs.c | 14 ++- src/radeon_display.c | 16 ++- src/radeon_dri.c | 6 +- src/radeon_driver.c | 314 ++++++++++++++++++++++++++++------------------- 6 files changed, 233 insertions(+), 166 deletions(-) diff --git a/src/radeon.h b/src/radeon.h index ce2fe191..8c399cd0 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -186,7 +186,6 @@ typedef struct _region { /* ------------------------------------- */ -#define RADEON_DEBUG 1 /* Turn off debugging output */ #define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ @@ -198,15 +197,7 @@ typedef struct _region { * for something else. */ -#if RADEON_DEBUG -#define RADEONTRACE(x) \ -do { \ - ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex); \ - ErrorF x; \ -} while(0) -#else -#define RADEONTRACE(x) do { } while(0) -#endif +#define RADEON_LOGLEVEL_DEBUG 4 /* Other macros */ diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 41859c4a..b739988f 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -134,9 +134,10 @@ void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries) INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; if (info->fifo_slots >= entries) return; } - RADEONTRACE(("FIFO timed out: %u entries, stat=0x%08x\n", - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - INREG(RADEON_RBBM_STATUS))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "FIFO timed out: %u entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "FIFO timed out, resetting engine...\n"); RADEONEngineReset(pScrn); @@ -165,8 +166,9 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) break; } if (i == RADEON_TIMEOUT) { - RADEONTRACE(("DC flush timeout: %x\n", - INREG(RADEON_RB3D_DSTCACHE_CTLSTAT))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "DC flush timeout: %x\n", + INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); } } @@ -296,9 +298,10 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONTRACE(("EngineRestore (%d/%d)\n", - info->CurrentLayout.pixel_code, - info->CurrentLayout.bitsPerPixel)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "EngineRestore (%d/%d)\n", + info->CurrentLayout.pixel_code, + info->CurrentLayout.bitsPerPixel); /* Setup engine location. This shouldn't be necessary since we * set them appropriately before any accel ops, but let's avoid @@ -347,9 +350,10 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONTRACE(("EngineInit (%d/%d)\n", - info->CurrentLayout.pixel_code, - info->CurrentLayout.bitsPerPixel)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "EngineInit (%d/%d)\n", + info->CurrentLayout.pixel_code, + info->CurrentLayout.bitsPerPixel); OUTREG(RADEON_RB3D_CNTL, 0); @@ -362,15 +366,17 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) case 24: info->datatype = 5; break; case 32: info->datatype = 6; break; default: - RADEONTRACE(("Unknown depth/bpp = %d/%d (code = %d)\n", - info->CurrentLayout.depth, - info->CurrentLayout.bitsPerPixel, - info->CurrentLayout.pixel_code)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Unknown depth/bpp = %d/%d (code = %d)\n", + info->CurrentLayout.depth, + info->CurrentLayout.bitsPerPixel, + info->CurrentLayout.pixel_code); } info->pitch = ((info->CurrentLayout.displayWidth / 8) * (info->CurrentLayout.pixel_bytes == 3 ? 3 : 1)); - RADEONTRACE(("Pitch for acceleration = %d\n", info->pitch)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Pitch for acceleration = %d\n", info->pitch); info->dp_gui_master_cntl = ((info->datatype << RADEON_GMC_DST_DATATYPE_SHIFT) diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c index 70f7ddc1..6a999af5 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -156,9 +156,10 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) #endif #if 0 - RADEONTRACE(("WaitForIdle (entering): %d entries, stat=0x%08x\n", - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - INREG(RADEON_RBBM_STATUS))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "WaitForIdle (entering): %d entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); #endif /* Wait for the engine to go idle */ @@ -171,9 +172,10 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) return; } } - RADEONTRACE(("Idle timed out: %u entries, stat=0x%08x\n", - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - INREG(RADEON_RBBM_STATUS))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Idle timed out: %u entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Idle timed out, resetting engine...\n"); RADEONEngineReset(pScrn); diff --git a/src/radeon_display.c b/src/radeon_display.c index fb345a9e..90fdc545 100644 --- a/src/radeon_display.c +++ b/src/radeon_display.c @@ -1941,8 +1941,10 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, RADEONInfoP OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - RADEONTRACE(("GRPH_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH_BUFFER_CNTL from %x to %x\n", + (unsigned int)info->SavedReg.grph_buffer_cntl, + INREG(RADEON_GRPH_BUFFER_CNTL)); if (mode2) { stop_req = mode2->HDisplay * info2->CurrentLayout.pixel_bytes / 16; @@ -1989,8 +1991,10 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, RADEONInfoP OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - RADEONTRACE(("GRPH2_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg.grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL))); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH2_BUFFER_CNTL from %x to %x\n", + (unsigned int)info->SavedReg.grph2_buffer_cntl, + INREG(RADEON_GRPH2_BUFFER_CNTL)); } } @@ -2266,7 +2270,9 @@ void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, RADEONConnector *pPort; if (!pScrn->vtSema) return; - RADEONTRACE(("RADEONDisplayPowerManagementSet(%d,0x%x)\n", PowerManagementMode, flags)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONDisplayPowerManagementSet(%d,0x%x)\n", + PowerManagementMode, flags); #ifdef XF86DRI if (info->CPStarted) DRILock(pScrn->pScreen, 0); diff --git a/src/radeon_dri.c b/src/radeon_dri.c index b09a8cf4..24e31ab5 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -1690,7 +1690,8 @@ void RADEONDRIStop(ScreenPtr pScreen) RADEONInfoPtr info = RADEONPTR(pScrn); RING_LOCALS; - RADEONTRACE(("RADEONDRIStop\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONDRIStop\n"); /* Stop the CP */ if (info->directRenderingInited) { @@ -1712,7 +1713,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) RADEONInfoPtr info = RADEONPTR(pScrn); drmRadeonInit drmInfo; - RADEONTRACE(("RADEONDRICloseScreen\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONDRICloseScreen\n"); if (info->irq) { drmCtlUninstHandler(info->drmFD); diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 933265f5..a8121951 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -626,7 +626,8 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn) if (info->FBDev) { info->FB = fbdevHWMapVidmem(pScrn); } else { - RADEONTRACE(("Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); info->FB = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER, info->PciTag, @@ -1285,10 +1286,14 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) */ info->mc_agp_location = 0xffffffc0; - RADEONTRACE(("RADEONInitMemoryMap() : \n")); - RADEONTRACE((" mem_size : 0x%08lx\n", mem_size)); - RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location)); - RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location)); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "RADEONInitMemoryMap() : \n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " mem_size : 0x%08lx\n", mem_size); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location); } static void RADEONGetVRamType(ScrnInfoPtr pScrn) @@ -3002,7 +3007,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) const char *s; MessageType from; - RADEONTRACE(("RADEONPreInit\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONPreInit\n"); if (pScrn->numEntities != 1) return FALSE; if (!RADEONGetRec(pScrn)) return FALSE; @@ -3793,8 +3799,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, char* s; #endif - RADEONTRACE(("RADEONScreenInit %lx %ld %d\n", - pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONScreenInit %lx %ld %d\n", + pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); info->accelOn = FALSE; #ifdef USE_XAA @@ -3911,13 +3918,15 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* Initial setup of surfaces */ if (!info->IsSecondary) { - RADEONTRACE(("Setting up initial surfaces\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Setting up initial surfaces\n"); RADEONChangeSurfaces(pScrn); } /* Memory manager setup */ - RADEONTRACE(("Setting up accel memmap\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Setting up accel memmap\n"); #ifdef USE_EXA if (info->useEXA) { @@ -4022,7 +4031,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } #endif - RADEONTRACE(("Initializing fb layer\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing fb layer\n"); /* Init fb layer */ if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset, @@ -4090,7 +4100,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); /* Backing store setup */ - RADEONTRACE(("Initializing backing store\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing backing store\n"); miInitializeBackingStore(pScreen); xf86SetBackingStore(pScreen); @@ -4110,7 +4121,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } if (info->directRenderingEnabled) { - RADEONTRACE(("DRI Finishing init !\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "DRI Finishing init !\n"); info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); } if (info->directRenderingEnabled) { @@ -4140,7 +4152,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* Make sure surfaces are allright since DRI setup may have changed them */ if (!info->IsSecondary) { - RADEONTRACE(("Setting up final surfaces\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Setting up final surfaces\n"); RADEONChangeSurfaces(pScrn); } @@ -4150,7 +4163,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* Enable aceleration */ if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - RADEONTRACE(("Initializing Acceleration\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing Acceleration\n"); if (RADEONAccelInit(pScreen)) { xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n"); info->accelOn = TRUE; @@ -4166,10 +4180,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } /* Init DPMS */ - RADEONTRACE(("Initializing DPMS\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing DPMS\n"); xf86DPMSInit(pScreen, RADEONDisplayPowerManagementSet, 0); - RADEONTRACE(("Initializing Cursor\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing Cursor\n"); /* Set Silken Mouse */ xf86SetSilkenMouse(pScreen); @@ -4207,7 +4223,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } /* Colormap setup */ - RADEONTRACE(("Initializing color map\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing color map\n"); if (!miCreateDefColormap(pScreen)) return FALSE; if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8, RADEONLoadPalette, NULL, @@ -4218,7 +4235,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; /* DGA setup */ - RADEONTRACE(("Initializing DGA\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing DGA\n"); RADEONDGAInit(pScreen); /* Wrap some funcs for MergedFB */ @@ -4235,7 +4253,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } /* Init Xv */ - RADEONTRACE(("Initializing Xv\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing Xv\n"); RADEONInitVideo(pScreen); if(info->MergedFB) @@ -4254,7 +4273,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (serverGeneration == 1) xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); - RADEONTRACE(("RADEONScreenInit finished\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONScreenInit finished\n"); return TRUE; } @@ -4268,9 +4288,12 @@ static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, unsigned char *RADEONMMIO = info->MMIO; int timeout; - RADEONTRACE(("RADEONRestoreMemMapRegisters() : \n")); - RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location)); - RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location)); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "RADEONRestoreMemMapRegisters() : \n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location); /* Write memory mapping registers only if their value change * since we must ensure no access is done while they are @@ -4281,7 +4304,8 @@ static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; CARD32 old_mc_status, status_idle; - RADEONTRACE((" Map Changed ! Applying ...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + " Map Changed ! Applying ...\n"); /* Make sure engine is idle. We assume the CCE is stopped * at this point @@ -4354,7 +4378,8 @@ static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, /* Make sure map fully reached the chip */ (void)INREG(RADEON_MC_FB_LOCATION); - RADEONTRACE((" Map applied, resetting engine ...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + " Map applied, resetting engine ...\n"); /* Reset the engine and HDP */ RADEONEngineReset(pScrn); @@ -4391,7 +4416,8 @@ static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, } } - RADEONTRACE(("Updating display base addresses...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Updating display base addresses...\n"); OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); if (pRADEONEnt->HasCRTC2) @@ -4402,7 +4428,8 @@ static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, /* More paranoia delays, wait 100ms */ usleep(100000); - RADEONTRACE(("Memory map updated.\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Memory map updated.\n"); } #ifdef XF86DRI @@ -4538,8 +4565,9 @@ static void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONTRACE(("Programming CRTC1, offset: 0x%08lx\n", - restore->crtc_offset)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Programming CRTC1, offset: 0x%08lx\n", + restore->crtc_offset); /* We prevent the CRTC from hitting the memory controller until * fully programmed @@ -4592,8 +4620,9 @@ static void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, unsigned char *RADEONMMIO = info->MMIO; CARD32 crtc2_gen_cntl; - RADEONTRACE(("Programming CRTC2, offset: 0x%08lx\n", - restore->crtc2_offset)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Programming CRTC2, offset: 0x%08lx\n", + restore->crtc2_offset); crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) & (RADEON_CRTC2_VSYNC_DIS | @@ -4798,15 +4827,17 @@ static void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, | RADEON_PPLL_ATOMIC_UPDATE_EN | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); - RADEONTRACE(("Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n", - restore->ppll_ref_div, - restore->ppll_div_3, - restore->htotal_cntl, - INPLL(pScrn, RADEON_PPLL_CNTL))); - RADEONTRACE(("Wrote: rd=%d, fd=%d, pd=%d\n", - restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, - (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n", + restore->ppll_ref_div, + restore->ppll_div_3, + restore->htotal_cntl, + INPLL(pScrn, RADEON_PPLL_CNTL)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Wrote: rd=%d, fd=%d, pd=%d\n", + restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, + restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, + (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); usleep(50000); /* Let the clock to lock */ @@ -4857,15 +4888,17 @@ static void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, | RADEON_P2PLL_ATOMIC_UPDATE_EN | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN)); - RADEONTRACE(("Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n", - restore->p2pll_ref_div, - restore->p2pll_div_0, - restore->htotal_cntl2, - INPLL(pScrn, RADEON_P2PLL_CNTL))); - RADEONTRACE(("Wrote: rd=%ld, fd=%ld, pd=%ld\n", - restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, - restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, - (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n", + restore->p2pll_ref_div, + restore->p2pll_div_0, + restore->htotal_cntl2, + INPLL(pScrn, RADEON_P2PLL_CNTL)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Wrote: rd=%ld, fd=%ld, pd=%ld\n", + restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, + restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, + (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16); usleep(5000); /* Let the clock to lock */ @@ -5092,7 +5125,9 @@ static void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) RADEONController* pCRTC1 = pRADEONEnt->Controller[0]; RADEONController* pCRTC2 = pRADEONEnt->Controller[1]; RADEONConnector *pPort; - RADEONTRACE(("RADEONRestoreMode(%p)\n", restore)); + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONRestoreMode(%p)\n", restore); /* For Non-dual head card, we don't have private field in the Entity */ if (!pRADEONEnt->HasCRTC2) { @@ -5338,14 +5373,16 @@ static void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL); save->vclk_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - RADEONTRACE(("Read: 0x%08x 0x%08x 0x%08lx\n", - save->ppll_ref_div, - save->ppll_div_3, - save->htotal_cntl)); - RADEONTRACE(("Read: rd=%d, fd=%d, pd=%d\n", - save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, - (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Read: 0x%08x 0x%08x 0x%08lx\n", + save->ppll_ref_div, + save->ppll_div_3, + save->htotal_cntl); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Read: rd=%d, fd=%d, pd=%d\n", + save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, + save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, + (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); } /* Read PLL registers */ @@ -5356,14 +5393,16 @@ static void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL); save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - RADEONTRACE(("Read: 0x%08lx 0x%08lx 0x%08lx\n", - save->p2pll_ref_div, - save->p2pll_div_0, - save->htotal_cntl2)); - RADEONTRACE(("Read: rd=%ld, fd=%ld, pd=%ld\n", - save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, - save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, - (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Read: 0x%08lx 0x%08lx 0x%08lx\n", + save->p2pll_ref_div, + save->p2pll_div_0, + save->htotal_cntl2); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Read: rd=%ld, fd=%ld, pd=%ld\n", + save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, + save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, + (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16); } /* Read palette data */ @@ -5391,7 +5430,8 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save) { RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONTRACE(("RADEONSaveMode(%p)\n", save)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSaveMode(%p)\n", save); if (info->IsSecondary) { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); @@ -5409,7 +5449,8 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save) /*memcpy(&info->ModeReg, &info->SavedReg, sizeof(RADEONSaveRec));*/ } - RADEONTRACE(("RADEONSaveMode returns %p\n", save)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSaveMode returns %p\n", save); } /* Save everything needed to restore the original VC state */ @@ -5419,7 +5460,9 @@ static void RADEONSave(ScrnInfoPtr pScrn) unsigned char *RADEONMMIO = info->MMIO; RADEONSavePtr save = &info->SavedReg; - RADEONTRACE(("RADEONSave\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSave\n"); + if (info->FBDev) { RADEONSaveMemMapRegisters(pScrn, save); fbdevHWSave(pScrn); @@ -5464,7 +5507,8 @@ static void RADEONRestore(ScrnInfoPtr pScrn) unsigned char *RADEONMMIO = info->MMIO; RADEONSavePtr restore = &info->SavedReg; - RADEONTRACE(("RADEONRestore\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONRestore\n"); #if X_BYTE_ORDER == X_BIG_ENDIAN RADEONWaitForFifo(pScrn, 1); @@ -6251,11 +6295,12 @@ static void RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, pll->reference_freq); save->post_div = post_div->divider; - RADEONTRACE(("dc=%ld, of=%ld, fd=%d, pd=%d\n", - save->dot_clock_freq, - save->pll_output_freq, - save->feedback_div, - save->post_div)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "dc=%ld, of=%ld, fd=%d, pd=%d\n", + save->dot_clock_freq, + save->pll_output_freq, + save->feedback_div, + save->post_div); save->ppll_ref_div = pll->reference_div; save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); @@ -6318,11 +6363,12 @@ static void RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, pll->reference_freq); save->post_div_2 = post_div->divider; - RADEONTRACE(("dc=%ld, of=%ld, fd=%d, pd=%d\n", - save->dot_clock_freq_2, - save->pll_output_freq_2, - save->feedback_div_2, - save->post_div_2)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "dc=%ld, of=%ld, fd=%d, pd=%d\n", + save->dot_clock_freq_2, + save->pll_output_freq_2, + save->feedback_div_2, + save->post_div_2); save->p2pll_ref_div = pll->reference_div; save->p2pll_div_0 = (save->feedback_div_2 | @@ -6356,23 +6402,23 @@ static Bool RADEONInit2(ScrnInfoPtr pScrn, DisplayModePtr crtc1, RADEONInfoPtr info0 = NULL; ScrnInfoPtr pScrn0 = NULL; -#if RADEON_DEBUG if (crtc1 && (crtc_mask & 1)) { - ErrorF("%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)", - crtc1->name, - crtc1->Clock/1000.0, - - crtc1->HDisplay, - crtc1->HSyncStart, - crtc1->HSyncEnd, - crtc1->HTotal, - - crtc1->VDisplay, - crtc1->VSyncStart, - crtc1->VSyncEnd, - crtc1->VTotal, - pScrn->depth, - pScrn->bitsPerPixel); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)", + crtc1->name, + crtc1->Clock/1000.0, + + crtc1->HDisplay, + crtc1->HSyncStart, + crtc1->HSyncEnd, + crtc1->HTotal, + + crtc1->VDisplay, + crtc1->VSyncStart, + crtc1->VSyncEnd, + crtc1->VTotal, + pScrn->depth, + pScrn->bitsPerPixel); if (crtc1->Flags & V_DBLSCAN) ErrorF(" D"); if (crtc1->Flags & V_CSYNC) ErrorF(" C"); if (crtc1->Flags & V_INTERLACE) ErrorF(" I"); @@ -6383,21 +6429,22 @@ static Bool RADEONInit2(ScrnInfoPtr pScrn, DisplayModePtr crtc1, ErrorF("\n"); } if (crtc2 && (crtc_mask & 2)) { - ErrorF("%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)", - crtc2->name, - crtc2->Clock/1000.0, - - crtc2->CrtcHDisplay, - crtc2->CrtcHSyncStart, - crtc2->CrtcHSyncEnd, - crtc2->CrtcHTotal, - - crtc2->CrtcVDisplay, - crtc2->CrtcVSyncStart, - crtc2->CrtcVSyncEnd, - crtc2->CrtcVTotal, - pScrn->depth, - pScrn->bitsPerPixel); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)", + crtc2->name, + crtc2->Clock/1000.0, + + crtc2->CrtcHDisplay, + crtc2->CrtcHSyncStart, + crtc2->CrtcHSyncEnd, + crtc2->CrtcHTotal, + + crtc2->CrtcVDisplay, + crtc2->CrtcVSyncStart, + crtc2->CrtcVSyncEnd, + crtc2->CrtcVTotal, + pScrn->depth, + pScrn->bitsPerPixel); if (crtc2->Flags & V_DBLSCAN) ErrorF(" D"); if (crtc2->Flags & V_CSYNC) ErrorF(" C"); if (crtc2->Flags & V_INTERLACE) ErrorF(" I"); @@ -6407,7 +6454,6 @@ static Bool RADEONInit2(ScrnInfoPtr pScrn, DisplayModePtr crtc1, if (crtc2->Flags & V_NVSYNC) ErrorF(" -V"); ErrorF("\n"); } -#endif if (crtc1 && (crtc_mask & 1)) info->Flags = crtc1->Flags; @@ -6467,7 +6513,8 @@ static Bool RADEONInit2(ScrnInfoPtr pScrn, DisplayModePtr crtc1, return FALSE; } - RADEONTRACE(("RADEONInit returns %p\n", save)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONInit returns %p\n", save); return TRUE; } @@ -6491,7 +6538,8 @@ static Bool RADEONModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode) { RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONTRACE(("RADEONModeInit()\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONModeInit()\n"); if (!RADEONInit(pScrn, mode, &info->ModeReg)) return FALSE; @@ -6513,7 +6561,8 @@ static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; Bool unblank; - RADEONTRACE(("RADEONSaveScreen(%d)\n", mode)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSaveScreen(%d)\n", mode); unblank = xf86IsUnblank(mode); if (unblank) SetTimeSinceLastInputEvent(); @@ -6560,7 +6609,8 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) } #endif - RADEONTRACE(("RADEONSwitchMode() !n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSwitchMode() !n"); if (info->allowColorTiling) { if (info->MergedFB) { @@ -6678,7 +6728,8 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, int clone) #endif #if 0 /* Verbose */ - RADEONTRACE(("RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone)); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone); #endif if (info->showCache && y) { @@ -6817,7 +6868,8 @@ Bool RADEONEnterVT(int scrnIndex, int flags) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - RADEONTRACE(("RADEONEnterVT\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONEnterVT\n"); if (INREG(RADEON_CONFIG_MEMSIZE) == 0) { /* Softboot V_BIOS */ xf86Int10InfoPtr pInt; @@ -6888,7 +6940,8 @@ void RADEONLeaveVT(int scrnIndex, int flags) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONSavePtr save = &info->ModeReg; - RADEONTRACE(("RADEONLeaveVT\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONLeaveVT\n"); #ifdef XF86DRI if (RADEONPTR(pScrn)->directRenderingInited) { DRILock(pScrn->pScreen, 0); @@ -6926,7 +6979,8 @@ void RADEONLeaveVT(int scrnIndex, int flags) RADEONRestore(pScrn); - RADEONTRACE(("Ok, leaving now...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Ok, leaving now...\n"); } /* Called at the end of each server generation. Restore the original @@ -6938,7 +6992,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONTRACE(("RADEONCloseScreen\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONCloseScreen\n"); /* Mark acceleration as stopped or we might try to access the engine at * wrong times, especially if we had DRI, after DRI has been stopped @@ -6971,7 +7026,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) RADEONRestore(pScrn); } - RADEONTRACE(("Disposing accel...\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Disposing accel...\n"); #ifdef USE_EXA if (info->exa) { exaDriverFini(pScreen); @@ -6991,14 +7047,17 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) } #endif /* USE_XAA */ - RADEONTRACE(("Disposing cusor info\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Disposing cusor info\n"); if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); info->cursor = NULL; - RADEONTRACE(("Disposing DGA\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Disposing DGA\n"); if (info->DGAModes) xfree(info->DGAModes); info->DGAModes = NULL; - RADEONTRACE(("Unmapping memory\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Unmapping memory\n"); RADEONUnmapMem(pScrn); pScrn->vtSema = FALSE; @@ -7015,7 +7074,8 @@ void RADEONFreeScreen(int scrnIndex, int flags) ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONTRACE(("RADEONFreeScreen\n")); + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONFreeScreen\n"); /* when server quits at PreInit, we don't need do this anymore*/ if (!info) return; -- cgit v1.2.3 From 8275151baac22c34149cef0b7d922771d24abc3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Mon, 21 May 2007 10:25:48 +0200 Subject: radeon: HW cursor cleanup. Don't needlessly turn the HW cursor on/off in RADEONLoadCursor*(). Besides cleaning up the code, this semms to avoid some HW cursor related 3D lockups, see https://bugs.freedesktop.org/show_bug.cgi?id=10815 . My best guess is that this is because the engine is now always idled before touching the CRTC registers. --- src/radeon_cursor.c | 64 +++++++++-------------------------------------------- src/radeon_reg.h | 2 +- 2 files changed, 12 insertions(+), 54 deletions(-) diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c index a45198ae..ec80dd87 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -71,8 +71,6 @@ static CARD32 mono_cursor_color[] = { #define CURSOR_WIDTH 64 #define CURSOR_HEIGHT 64 -#define COMMON_CURSOR_SWAPPING_START() RADEON_SYNC(info, pScrn) - /* * The cursor bits are always 32bpp. On MSBFirst buses, * configure byte swapping to swap 32 bit units when writing @@ -84,7 +82,6 @@ static CARD32 mono_cursor_color[] = { #define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO; #define CURSOR_SWAPPING_START() \ do { \ - COMMON_CURSOR_SWAPPING_START(); \ OUTREG(RADEON_SURFACE_CNTL, \ (info->ModeReg.surface_cntl | \ RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \ @@ -96,10 +93,7 @@ static CARD32 mono_cursor_color[] = { #else #define CURSOR_SWAPPING_DECL_MMIO -#define CURSOR_SWAPPING_START() \ - do { \ - COMMON_CURSOR_SWAPPING_START(); \ - } while (0) +#define CURSOR_SWAPPING_START() #define CURSOR_SWAPPING_END() #endif @@ -205,25 +199,11 @@ static void RADEONLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image) unsigned char *RADEONMMIO = info->MMIO; CARD8 *s = (CARD8 *)(pointer)image; CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); - CARD32 save1 = 0; - CARD32 save2 = 0; CARD8 chunk; CARD32 i, j; RADEONCTRACE(("RADEONLoadCursorImage (at %x)\n", info->cursor_offset)); - if (!info->IsSecondary) { - save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20); - save1 |= (CARD32) (2 << 20); - OUTREG(RADEON_CRTC_GEN_CNTL, save1 & (CARD32)~RADEON_CRTC_CUR_EN); - } - - if (info->IsSecondary || info->MergedFB) { - save2 = INREG(RADEON_CRTC2_GEN_CNTL) & ~(CARD32) (3 << 20); - save2 |= (CARD32) (2 << 20); - OUTREG(RADEON_CRTC2_GEN_CNTL, save2 & (CARD32)~RADEON_CRTC2_CUR_EN); - } - #ifdef ARGB_CURSOR info->cursor_argb = FALSE; #endif @@ -237,23 +217,18 @@ static void RADEONLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image) * (which actually bit swaps the image) to make the bits LSBFirst */ CURSOR_SWAPPING_START(); + #define ARGB_PER_CHUNK (8 * sizeof (chunk) / 2) for (i = 0; i < (CURSOR_WIDTH * CURSOR_HEIGHT / ARGB_PER_CHUNK); i++) { chunk = *s++; for (j = 0; j < ARGB_PER_CHUNK; j++, chunk >>= 2) *d++ = mono_cursor_color[chunk & 3]; } + CURSOR_SWAPPING_END(); info->cursor_bg = mono_cursor_color[2]; info->cursor_fg = mono_cursor_color[3]; - - if (!info->IsSecondary) - OUTREG(RADEON_CRTC_GEN_CNTL, save1); - - if (info->IsSecondary || info->MergedFB) - OUTREG(RADEON_CRTC2_GEN_CNTL, save2); - } /* Hide hardware cursor. */ @@ -264,6 +239,8 @@ static void RADEONHideCursor(ScrnInfoPtr pScrn) RADEONCTRACE(("RADEONHideCursor\n")); + RADEON_SYNC(info, pScrn); + if (info->IsSecondary || info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN); @@ -279,13 +256,15 @@ static void RADEONShowCursor(ScrnInfoPtr pScrn) RADEONCTRACE(("RADEONShowCursor\n")); + RADEON_SYNC(info, pScrn); + if (info->IsSecondary || info->MergedFB) - OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN, - ~RADEON_CRTC2_CUR_EN); + OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN | 2 << 20, + ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_CUR_MODE_MASK)); if (!info->IsSecondary) - OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN, - ~RADEON_CRTC_CUR_EN); + OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN | 2 << 20, + ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); } /* Determine if hardware cursor is in use. */ @@ -314,25 +293,11 @@ static void RADEONLoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs) unsigned char *RADEONMMIO = info->MMIO; CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); int x, y, w, h; - CARD32 save1 = 0; - CARD32 save2 = 0; CARD32 *image = pCurs->bits->argb; CARD32 *i; RADEONCTRACE(("RADEONLoadCursorARGB\n")); - if (!info->IsSecondary) { - save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20); - save1 |= (CARD32) (2 << 20); - OUTREG(RADEON_CRTC_GEN_CNTL, save1 & (CARD32)~RADEON_CRTC_CUR_EN); - } - - if (info->IsSecondary || info->MergedFB) { - save2 = INREG(RADEON_CRTC2_GEN_CNTL) & ~(CARD32) (3 << 20); - save2 |= (CARD32) (2 << 20); - OUTREG(RADEON_CRTC2_GEN_CNTL, save2 & (CARD32)~RADEON_CRTC2_CUR_EN); - } - #ifdef ARGB_CURSOR info->cursor_argb = TRUE; #endif @@ -361,13 +326,6 @@ static void RADEONLoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs) *d++ = 0; CURSOR_SWAPPING_END (); - - if (!info->IsSecondary) - OUTREG(RADEON_CRTC_GEN_CNTL, save1); - - if (info->IsSecondary || info->MergedFB) - OUTREG(RADEON_CRTC2_GEN_CNTL, save2); - } #endif diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 0d5e5863..81acd468 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -308,7 +308,7 @@ # define RADEON_CRTC_CSYNC_EN (1 << 4) # define RADEON_CRTC_ICON_EN (1 << 15) # define RADEON_CRTC_CUR_EN (1 << 16) -# define RADEON_CRTC_CUR_MODE_MASK (7 << 17) +# define RADEON_CRTC_CUR_MODE_MASK (7 << 20) # define RADEON_CRTC_EXT_DISP_EN (1 << 24) # define RADEON_CRTC_EN (1 << 25) # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) -- cgit v1.2.3 From 975da595f032c145ad74079ff8edeaead779dc7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 22 May 2007 10:56:47 +0200 Subject: radeon: Provide new DRI texOffsetStart hook when available with EXA. --- src/radeon.h | 1 + src/radeon_dri.c | 16 ++++++++++++++++ src/radeon_exa.c | 17 +++++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/src/radeon.h b/src/radeon.h index 8c399cd0..3ea44f3a 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -851,6 +851,7 @@ extern Bool RADEONAccelInit(ScreenPtr pScreen); extern Bool RADEONSetupMemEXA (ScreenPtr pScreen); extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); #ifdef XF86DRI +extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type); extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 *pitch_offset); diff --git a/src/radeon_dri.c b/src/radeon_dri.c index 24e31ab5..39393f54 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -1475,6 +1475,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->createDummyCtx = TRUE; pDRIInfo->createDummyCtxPriv = FALSE; +#ifdef USE_EXA + if (info->useEXA) { +#if DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3 + int major, minor, patch; + + DRIQueryVersion(&major, &minor, &patch); + + if (minor >= 3) +#endif +#if DRIINFO_MAJOR_VERSION > 5 || \ + (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3) + pDRIInfo->texOffsetStart = RADEONTexOffsetStart; +#endif + } +#endif + if (!DRIScreenInit(pScreen, pDRIInfo, &info->drmFD)) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[dri] DRIScreenInit failed. Disabling DRI.\n"); diff --git a/src/radeon_exa.c b/src/radeon_exa.c index f9bcaceb..d074f08a 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -496,3 +496,20 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) return TRUE; } + +#ifdef XF86DRI + +#ifndef ExaOffscreenMarkUsed +extern void ExaOffscreenMarkUsed(PixmapPtr); +#endif + +unsigned long long +RADEONTexOffsetStart(PixmapPtr pPix) +{ + exaMoveInPixmap(pPix); + ExaOffscreenMarkUsed(pPix); + + return RADEONPTR(xf86Screens[pPix->drawable.pScreen->myNum])->fbLocation + + exaGetPixmapOffset(pPix); +} +#endif -- cgit v1.2.3 From 5aa603bcabbb077dec169c48438c2e2ebe1195d7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 29 May 2007 07:23:24 +1000 Subject: rs480: only has single dac --- src/radeon_driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/radeon_driver.c b/src/radeon_driver.c index a8121951..b0e40370 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1720,7 +1720,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) case PCI_CHIP_RS482_5974: info->ChipFamily = CHIP_FAMILY_RS400; info->IsIGP = TRUE; - /*info->HasSingleDAC = TRUE;*/ /* ??? */ + info->HasSingleDAC = TRUE; break; case PCI_CHIP_RV410_564A: -- cgit v1.2.3 From 104105fee5c3945d3f210e6a4cb73ab492c61543 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 29 May 2007 19:09:33 +1000 Subject: rs480: make second crtc work with magic number in magic register. I've no idea why or what this does. --- src/radeon.h | 1 + src/radeon_driver.c | 31 ++++++++++++++++++++----------- src/radeon_reg.h | 2 ++ 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/src/radeon.h b/src/radeon.h index 3ea44f3a..3e79c1b2 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -318,6 +318,7 @@ typedef struct { CARD32 tv_dac_cntl; + CARD32 rs480_unk_e38; } RADEONSaveRec, *RADEONSavePtr; typedef struct { diff --git a/src/radeon_driver.c b/src/radeon_driver.c index b0e40370..a3d8a033 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -4664,6 +4664,9 @@ static void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); + if (info->ChipFamily == CHIP_FAMILY_RS400) { + OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38); + } OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); } @@ -4858,11 +4861,10 @@ static void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, OUTPLLP(pScrn, RADEON_P2PLL_CNTL, RADEON_P2PLL_RESET - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN, + | RADEON_P2PLL_ATOMIC_UPDATE_EN, ~(RADEON_P2PLL_RESET - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN)); + | RADEON_P2PLL_ATOMIC_UPDATE_EN)); + OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, restore->p2pll_ref_div, @@ -4885,17 +4887,16 @@ static void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 0, ~(RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN)); + | RADEON_P2PLL_ATOMIC_UPDATE_EN)); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n", + "Wrote2: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n", restore->p2pll_ref_div, restore->p2pll_div_0, restore->htotal_cntl2, INPLL(pScrn, RADEON_P2PLL_CNTL)); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Wrote: rd=%ld, fd=%ld, pd=%ld\n", + "Wrote2: rd=%ld, fd=%ld, pd=%ld\n", restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16); @@ -5362,6 +5363,9 @@ static void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); + if (info->ChipFamily == CHIP_FAMILY_RS400) + save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38); + save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); } @@ -5636,10 +5640,10 @@ static void RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEON_TV_DAC_GDACPD); } /* FIXME: doesn't make sense, this just replaces the previous value... */ - save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK | + save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | - RADEON_TV_DAC_STD_PS2 | - info->tv_dac_adj); + RADEON_TV_DAC_STD_PS2); + // info->tv_dac_adj); } static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, @@ -6236,6 +6240,11 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, } #endif + if (info->ChipFamily == CHIP_FAMILY_RS400) { + save->rs480_unk_e38 = info->SavedReg.rs480_unk_e38 & ~(0x300); + save->rs480_unk_e38 |= 0x100; + } + return TRUE; } diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 81acd468..476c56b6 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3126,4 +3126,6 @@ # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) # define RADEON_TVPLL_SLEEP (1 << 3) # define RADEON_TVPLL_REFCLK_SEL (1 << 4) + +#define RADEON_RS480_UNK_e38 0xe38 #endif -- cgit v1.2.3 From bff809dc8ed07ac39e9b576a87916486a5e37156 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 30 May 2007 08:02:26 +1000 Subject: rs480: more unknown regs Hardcode the values from a working fglrx run, this works for me now I've no idea what it might do for anyone else --- src/radeon.h | 3 +++ src/radeon_driver.c | 15 ++++++++++++--- src/radeon_reg.h | 4 ++++ 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/radeon.h b/src/radeon.h index 3e79c1b2..88402df5 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -318,7 +318,10 @@ typedef struct { CARD32 tv_dac_cntl; + CARD32 rs480_unk_e30; + CARD32 rs480_unk_e34; CARD32 rs480_unk_e38; + CARD32 rs480_unk_e3c; } RADEONSaveRec, *RADEONSavePtr; typedef struct { diff --git a/src/radeon_driver.c b/src/radeon_driver.c index a3d8a033..5eca577a 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -4665,7 +4665,10 @@ static void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); if (info->ChipFamily == CHIP_FAMILY_RS400) { + OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30); + OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34); OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38); + OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c); } OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); @@ -5363,8 +5366,12 @@ static void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); - if (info->ChipFamily == CHIP_FAMILY_RS400) + if (info->ChipFamily == CHIP_FAMILY_RS400) { + save->rs480_unk_e30 = INREG(RADEON_RS480_UNK_e30); + save->rs480_unk_e34 = INREG(RADEON_RS480_UNK_e34); save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38); + save->rs480_unk_e3c = INREG(RADEON_RS480_UNK_e3c); + } save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); } @@ -6241,8 +6248,10 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, #endif if (info->ChipFamily == CHIP_FAMILY_RS400) { - save->rs480_unk_e38 = info->SavedReg.rs480_unk_e38 & ~(0x300); - save->rs480_unk_e38 |= 0x100; + save->rs480_unk_e30 = 0x105DC1CC; /* because I'm worth it */ + save->rs480_unk_e34 = 0x2749D000; /* AMD really should */ + save->rs480_unk_e38 = 0x29ca71dc; /* release docs */ + save->rs480_unk_e3c = 0x28FBC3AC; /* this is so a trade secret */ } return TRUE; diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 476c56b6..01bcec80 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3127,5 +3127,9 @@ # define RADEON_TVPLL_SLEEP (1 << 3) # define RADEON_TVPLL_REFCLK_SEL (1 << 4) +#define RADEON_RS480_UNK_e30 0xe30 +#define RADEON_RS480_UNK_e34 0xe34 #define RADEON_RS480_UNK_e38 0xe38 +#define RADEON_RS480_UNK_e3c 0xe3c + #endif -- cgit v1.2.3 From 5337e7bd0069a3f2c4ab22b21a19471427ad3d81 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 30 May 2007 08:10:44 +1000 Subject: radeon: add bios quirk for nx6125 monid --- src/radeon_bios.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/radeon_bios.c b/src/radeon_bios.c index dd3d0a7a..e62fb257 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c @@ -34,12 +34,28 @@ #include "xf86.h" #include "xf86_OSproc.h" +#include "xf86PciInfo.h" #include "radeon.h" #include "radeon_reg.h" #include "radeon_macros.h" #include "radeon_probe.h" #include "vbe.h" +int RADEONBIOSApplyConnectorQuirks(ScrnInfoPtr pScrn, int connector_found) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + + /* quirk for compaq nx6125 - the bios lies about the VGA DDC */ + if (info->PciInfo->subsysVendor == PCI_VENDOR_HP) { + if (info->PciInfo->subsysCard == 0x308b) { + if (pRADEONEnt->PortInfo[1]->DDCType == DDC_CRT2) + pRADEONEnt->PortInfo[1]->DDCType = DDC_MONID; + } + } + return connector_found; +} + /* Read the Video BIOS block and the FP registers (if applicable). */ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { @@ -313,6 +329,8 @@ Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) connector_found = 1; } + connector_found = RADEONBIOSApplyConnectorQuirks(pScrn, connector_found); + if (connector_found == 0) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No connector found in Connector Info Table.\n"); } else { -- cgit v1.2.3 From 4c61c0ee91a2ffeefce30972a584486f1df1d1ae Mon Sep 17 00:00:00 2001 From: Matthieu Herrb Date: Tue, 29 May 2007 21:35:35 -0600 Subject: Fix build without XF86DRI --- src/radeon_driver.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 5eca577a..25921ad3 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -3799,15 +3799,23 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, char* s; #endif +#ifdef XF86DRI xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONScreenInit %lx %ld %d\n", pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); +#else + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONScreenInit %lx %ld\n", + pScrn->memPhysBase, pScrn->fbOffset); +#endif info->accelOn = FALSE; #ifdef USE_XAA info->accel = NULL; #endif +#ifdef XF86DRI pScrn->fbOffset = info->frontOffset; +#endif if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; if (!RADEONMapMem(pScrn)) return FALSE; @@ -3997,6 +4005,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* Setup DRI after visuals have been established, but before fbScreenInit is * called. fbScreenInit will eventually call the driver's InitGLXVisuals * call back. */ +#ifdef XF86DRI if (info->directRenderingEnabled) { /* FIXME: When we move to dynamic allocation of back and depth * buffers, we will want to revisit the following check for 3 @@ -4020,7 +4029,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } -#if defined(XF86DRI) /* Tell DRI about new memory map */ if (info->directRenderingEnabled && info->newMemoryMap) { if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) { -- cgit v1.2.3