From 9645838c57f6b40837fdce23ce7f9faefb3d9966 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Wed, 8 Jul 2009 19:18:02 +0200 Subject: Further non-KMS fixes / cleanups. Only compile tested. --- src/radeon.h | 34 +++++++++------------------------- src/radeon_exa.c | 6 ++++++ src/radeon_exa_funcs.c | 37 ++++++++++++++++--------------------- src/radeon_exa_render.c | 8 ++------ src/radeon_textured_videofuncs.c | 20 ++++++++++++++++---- 5 files changed, 49 insertions(+), 56 deletions(-) diff --git a/src/radeon.h b/src/radeon.h index c5b2cc27..ad9a9088 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -1519,6 +1519,13 @@ do { \ #endif /* XF86DRI */ #if defined(XF86DRI) && defined(USE_EXA) + +#ifdef XF86DRM_MODE +#define CS_FULL(cs) ((cs)->cdw > 15 * 1024) +#else +#define CS_FULL(cs) FALSE +#endif + #define RADEON_SWITCH_TO_2D() \ do { \ uint32_t flush = 0; \ @@ -1537,7 +1544,7 @@ do { \ } \ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ } while (0); -# ifdef XF86DRM_MODE + #define RADEON_SWITCH_TO_3D() \ do { \ uint32_t flush = 0; \ @@ -1546,7 +1553,7 @@ do { \ flush = 1; \ break; \ case EXA_ENGINEMODE_2D: \ - flush = !info->cs || info->cs->cdw > 15 * 1024; \ + flush = !info->cs || CS_FULL(info->cs); \ case EXA_ENGINEMODE_3D: \ break; \ } \ @@ -1560,29 +1567,6 @@ do { \ RADEONInit3DEngine(pScrn); \ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ } while (0); -# else -#define RADEON_SWITCH_TO_3D() \ -do { \ - uint32_t flush = 0; \ - switch (info->accel_state->engineMode) { \ - case EXA_ENGINEMODE_UNKNOWN: \ - case EXA_ENGINEMODE_2D: \ - flush = 1; \ - break; \ - case EXA_ENGINEMODE_3D: \ - break; \ - } \ - if (flush) { \ - if (info->cs) \ - radeon_cs_flush_indirect(pScrn); \ - else if (info->directRenderingEnabled) \ - RADEONCPFlushIndirect(pScrn, 1); \ - } \ - if (!info->accel_state->XInited3D) \ - RADEONInit3DEngine(pScrn); \ - info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ -} while (0); -# endif #else #define RADEON_SWITCH_TO_2D() #define RADEON_SWITCH_TO_3D() diff --git a/src/radeon_exa.c b/src/radeon_exa.c index e7f1e9ca..4f1f9eac 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -120,6 +120,9 @@ static __inline__ uint32_t F_TO_DW(float val) return tmp.l; } + +#ifdef XF86DRM_MODE + static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain) { struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix); @@ -127,6 +130,9 @@ static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int r radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain); } +#endif /* XF86DRM_MODE */ + + /* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we * require src and dest datatypes to be equal. */ diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c index 4b75299d..19adffbd 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c @@ -152,8 +152,6 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); uint32_t datatype, dst_pitch_offset; - struct radeon_exa_pixmap_priv *driver_priv; - int ret; TRACE; @@ -166,7 +164,10 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) RADEON_SWITCH_TO_2D(); +#ifdef XF86DRM_MODE if (info->cs) { + struct radeon_exa_pixmap_priv *driver_priv; + int ret; radeon_cs_space_reset_bos(info->cs); @@ -176,8 +177,12 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) ret = radeon_cs_space_check(info->cs); if (ret) RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n")); - } + driver_priv = exaGetPixmapDriverPrivate(pPix); + if (driver_priv) + info->state_2d.dst_bo = driver_priv->bo; + } +#endif info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); @@ -197,10 +202,6 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) info->state_2d.src_pitch_offset = 0; info->state_2d.src_bo = NULL; - driver_priv = exaGetPixmapDriverPrivate(pPix); - if (driver_priv) - info->state_2d.dst_bo = driver_priv->bo; - info->accel_state->dst_pix = pPix; FUNC_NAME(Emit2DState)(pScrn, RADEON_2D_EXA_SOLID); @@ -217,12 +218,8 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2) TRACE; -#ifdef ACCEL_CP - if (info->cs -#ifdef XF86DRM_MODE - && info->cs->cdw > 15 * 1024 -#endif - ) { +#if defined(ACCEL_CP) && defined(XF86DRM_MODE) + if (info->cs && CS_FULL(info->cs)) { FUNC_NAME(RADEONDone2D)(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); FUNC_NAME(Emit2DState)(pScrn, RADEON_2D_EXA_SOLID); @@ -277,13 +274,14 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, { RINFO_FROM_SCREEN(pDst->drawable.pScreen); uint32_t datatype, src_pitch_offset, dst_pitch_offset; - struct radeon_exa_pixmap_priv *driver_priv; - int ret; TRACE; RADEON_SWITCH_TO_2D(); +#ifdef XF86DRM_MODE if (info->cs) { + struct radeon_exa_pixmap_priv *driver_priv; + int ret; radeon_cs_space_reset_bos(info->cs); @@ -299,6 +297,7 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, if (ret) RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n")); } +#endif info->accel_state->xdir = xdir; info->accel_state->ydir = ydir; @@ -330,12 +329,8 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, TRACE; -#ifdef ACCEL_CP - if (info->cs -#ifdef XF86DRM_MODE - && info->cs->cdw > 15 * 1024 -#endif - ) { +#if defined(ACCEL_CP) && defined(XF86DRM_MODE) + if (info->cs && CS_FULL(info->cs)) { FUNC_NAME(RADEONDone2D)(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); FUNC_NAME(Emit2DState)(pScrn, RADEON_2D_EXA_COPY); diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index 73f8ee94..641ea1f2 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -2115,12 +2115,8 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn, /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ -#ifdef ACCEL_CP - if (info->cs -#ifdef XF86DRM_MODE - && info->cs->cdw > 15 * 1024 -#endif - ) { +#if defined(ACCEL_CP) && defined(XF86DRM_MODE) + if (info->cs && CS_FULL(info->cs)) { FUNC_NAME(RadeonDoneComposite)(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); info->accel_state->exa->PrepareComposite(info->accel_state->composite_op, diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c index b814921f..6e8b3f97 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -100,10 +100,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv int dstxoff, dstyoff, pixel_shift, vtx_count; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); - int ret; ACCEL_PREAMBLE(); +#ifdef XF86DRM_MODE if (info->cs) { + int ret; + radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); @@ -119,6 +121,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv return; } } +#endif pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; @@ -486,10 +489,12 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) int ref = pPriv->transform_index; float ucscale = 0.25, vcscale = 0.25; Bool needux8 = FALSE, needvx8 = FALSE; - int ret; ACCEL_PREAMBLE(); +#ifdef XF86DRM_MODE if (info->cs) { + int ret; + radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); @@ -505,6 +510,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) return; } } +#endif pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; @@ -1025,10 +1031,12 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) int dstxoff, dstyoff, pixel_shift, vtx_count; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); - int ret; ACCEL_PREAMBLE(); +#ifdef XF86DRM_MODE if (info->cs) { + int ret; + radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); @@ -1044,6 +1052,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) return; } } +#endif pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; @@ -2473,10 +2482,12 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) int dstxoff, dstyoff, pixel_shift, vtx_count; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); - int ret; ACCEL_PREAMBLE(); +#ifdef XF86DRM_MODE if (info->cs) { + int ret; + radeon_cs_space_reset_bos(info->cs); radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); @@ -2492,6 +2503,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) return; } } +#endif pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; -- cgit v1.2.3