From e843faf355c864beab81e74f0e39f8ad53d4c2bf Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Sep 2010 19:30:35 -0400 Subject: radeon: fix fbLocation for >32 bit MC addresses If the fbLocation was at an address >32 bits, we'd fail. Change fbLocation to uint64_t and properly cast when needed. --- src/atombios_crtc.c | 24 ++++++++++++++---------- src/radeon.h | 2 +- src/radeon_cursor.c | 12 +++++++----- src/radeon_driver.c | 8 ++++---- src/radeon_video.c | 2 +- 5 files changed, 27 insertions(+), 21 deletions(-) diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index d0ffa07f..651b3d78 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -727,7 +727,7 @@ static void evergreen_set_base_format(xf86CrtcPtr crtc, RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation; + uint64_t fb_location = crtc->scrn->fbOffset + info->fbLocation; uint32_t fb_format; uint32_t fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); @@ -787,8 +787,10 @@ static void evergreen_set_base_format(xf86CrtcPtr crtc, } - OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); - OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); + OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, + (fb_location >> 32) & 0xf); + OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, + (fb_location >> 32) & 0xf); OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, @@ -828,7 +830,7 @@ static void avivo_set_base_format(xf86CrtcPtr crtc, RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation; + uint64_t fb_location = crtc->scrn->fbOffset + info->fbLocation; uint32_t fb_format; #if X_BYTE_ORDER == X_BIG_ENDIAN uint32_t fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; @@ -875,15 +877,17 @@ static void avivo_set_base_format(xf86CrtcPtr crtc, if (info->ChipFamily >= CHIP_FAMILY_RV770) { if (radeon_crtc->crtc_id) { - OUTREG(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); - OUTREG(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); + OUTREG(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf); + OUTREG(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf); } else { - OUTREG(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); - OUTREG(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); + OUTREG(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf); + OUTREG(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf); } } - OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); - OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); + OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, + fb_location & 0xffffffff); + OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, + fb_location & 0xffffffff); OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); #if X_BYTE_ORDER == X_BIG_ENDIAN diff --git a/src/radeon.h b/src/radeon.h index 134a4cf2..7a3f5b66 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -832,7 +832,7 @@ typedef struct { unsigned long long LinearAddr; /* Frame buffer physical address */ unsigned long long MMIOAddr; /* MMIO region physical address */ unsigned long long BIOSAddr; /* BIOS physical address */ - uint32_t fbLocation; + uint64_t fbLocation; uint32_t gartLocation; uint32_t mc_fb_location; uint32_t mc_agp_location; diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c index 8eff9d1f..9fa2d805 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -106,11 +106,12 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); if (enable) { + uint64_t location = info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset; if (info->ChipFamily >= CHIP_FAMILY_RV770) { if (radeon_crtc->crtc_id) - OUTREG(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); + OUTREG(R700_D2CUR_SURFACE_ADDRESS_HIGH, (location >> 32) & 0xf); else - OUTREG(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); + OUTREG(R700_D1CUR_SURFACE_ADDRESS_HIGH, (location >> 32) & 0xf); } OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset); @@ -152,10 +153,11 @@ evergreen_setup_cursor(xf86CrtcPtr crtc, Bool enable) EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); if (enable) { - OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); + uint64_t location = info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset; + OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, + (location >> 32) & 0xf); OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, - (info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset) - & EVERGREEN_CUR_SURFACE_ADDRESS_MASK); + location & EVERGREEN_CUR_SURFACE_ADDRESS_MASK); OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, EVERGREEN_CURSOR_EN | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); } diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 7d6c32d7..6efb1729 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1517,9 +1517,9 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) } } if (info->ChipFamily >= CHIP_FAMILY_R600) { - info->fbLocation = (info->mc_fb_location & 0xffff) << 24; + info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 24; } else { - info->fbLocation = (info->mc_fb_location & 0xffff) << 16; + info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 16; } /* Just disable the damn AGP apertures for now, it may be * re-enabled later by the DRM @@ -4218,9 +4218,9 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) info->mc_fb_location = fb; info->mc_agp_location = agp; if (info->ChipFamily >= CHIP_FAMILY_R600) - info->fbLocation = (info->mc_fb_location & 0xffff) << 24; + info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 24; else - info->fbLocation = (info->mc_fb_location & 0xffff) << 16; + info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 16; info->accel_state->dst_pitch_offset = (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) diff --git a/src/radeon_video.c b/src/radeon_video.c index 1a42951c..f28e7afa 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -2759,7 +2759,7 @@ RADEONDisplayVideo( OUTREG(RADEON_OV0_P3_X_START_END, (src_w + leftuv - 1) | (leftuv << 16)); if (info->ModeReg->ov0_base_addr != (info->fbLocation + base_offset)) { ErrorF("Changing OV0_BASE_ADDR from 0x%08x to 0x%08x\n", - info->ModeReg->ov0_base_addr, info->fbLocation + base_offset); + info->ModeReg->ov0_base_addr, (uint32_t)info->fbLocation + base_offset); info->ModeReg->ov0_base_addr = info->fbLocation + base_offset; OUTREG(RADEON_OV0_BASE_ADDR, info->ModeReg->ov0_base_addr); } -- cgit v1.2.3