From 212e152536c4325e6799018891d9aee132681f48 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 22 Feb 2010 17:27:24 -0500 Subject: radeon: update new pll algo - add support for pre-avivo chips - add support for fixed post/ref dividers - add support for non-fractional fb dividers By default avivo chips use the new algo and pre-avivo chips use the old algo. Use the "NewPLL" option to toggle between them (set to TRUE for the new algo, FALSE for the old). --- src/legacy_crtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/legacy_crtc.c') diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index 0ad762b7..e4c1f043 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -1223,7 +1223,7 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, return; } - RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags); + RADEONComputePLL(pScrn, pll, mode->Clock, &freq, &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags); for (post_div = &post_divs[0]; post_div->divider; ++post_div) { if (post_div->divider == post_divider) @@ -1303,7 +1303,7 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, return; } - RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags); + RADEONComputePLL(pScrn, pll, mode->Clock, &freq, &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags); for (post_div = &post_divs[0]; post_div->divider; ++post_div) { if (post_div->divider == post_divider) -- cgit v1.2.3