From fa98f424de739be2c6005b740a74bbf1ee968a8b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 2 Mar 2009 02:28:57 -0500 Subject: R6xx/R7xx Xv: combine packed and planar shaders use a bool const to select the tex fetch routine --- src/r600_exa.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'src/r600_exa.c') diff --git a/src/r600_exa.c b/src/r600_exa.c index a44b6118..70c59b22 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -246,7 +246,8 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) ps_alu_consts[2] = (float)b / 255; /* B */ ps_alu_consts[3] = (float)a / 255; /* A */ } - set_alu_consts(pScrn, accel_state->ib, 0, sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); + set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps, + sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); accel_state->vb_index = 0; @@ -2027,13 +2028,9 @@ R600LoadShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen) accel_state->xv_vs_offset = 4096; R600_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4); - /* xv ps packed --------------------------------------- */ - accel_state->xv_ps_offset_packed = 4608; - R600_xv_ps_packet(ChipSet, shader + accel_state->xv_ps_offset_packed / 4); - - /* xv ps planar ---------------------------------- */ - accel_state->xv_ps_offset_planar = 5120; - R600_xv_ps_planar(ChipSet, shader + accel_state->xv_ps_offset_planar / 4); + /* xv ps --------------------------------------- */ + accel_state->xv_ps_offset = 4608; + R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4); return TRUE; } -- cgit v1.2.3