From 6559b6e28bf111b64c3aeb5ec1260acfeb3e0b7f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 15 Jun 2012 17:05:54 +0100 Subject: radeon: drop offset member of r600 accel object This is always 0 now. Signed-off-by: Dave Airlie --- src/r600_textured_videofuncs.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) (limited to 'src/r600_textured_videofuncs.c') diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c index a4a67f2a..970ab8e6 100644 --- a/src/r600_textured_videofuncs.c +++ b/src/r600_textured_videofuncs.c @@ -164,8 +164,6 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) CLEAR (vs_conf); CLEAR (ps_conf); - dst_obj.offset = 0; - src_obj.offset = 0; dst_obj.bo = radeon_get_pixmap_bo(pPixmap); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); dst_obj.surface = radeon_get_pixmap_surface(pPixmap); @@ -259,8 +257,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.pitch = accel_state->src_obj[0].pitch; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; - tex_res.base = accel_state->src_obj[0].offset; - tex_res.mip_base = accel_state->src_obj[0].offset; + tex_res.base = 0; + tex_res.mip_base = 0; tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; @@ -307,8 +305,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; - tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset; - tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset; + tex_res.base = pPriv->planev_offset; + tex_res.mip_base = pPriv->planev_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; @@ -330,8 +328,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; - tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset; - tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset; + tex_res.base = pPriv->planeu_offset; + tex_res.mip_base = pPriv->planeu_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; @@ -353,8 +351,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.pitch = accel_state->src_obj[0].pitch >> 1; tex_res.depth = 0; tex_res.dim = SQ_TEX_DIM_2D; - tex_res.base = accel_state->src_obj[0].offset; - tex_res.mip_base = accel_state->src_obj[0].offset; + tex_res.base = 0; + tex_res.mip_base = 0; tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; @@ -397,7 +395,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; - cb_conf.base = accel_state->dst_obj.offset; + cb_conf.base = 0; cb_conf.bo = accel_state->dst_obj.bo; cb_conf.surface = accel_state->dst_obj.surface; -- cgit v1.2.3