From 68158124366db883a901e960fe5f05f8df5efa42 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 19 Feb 2008 19:51:18 +1100 Subject: rs690: initial rs690 rotate suffers same problem as r500 with clipping --- src/radeon_exa_render.c | 78 +++++++++++++++++++++++++++++++------------------ 1 file changed, 50 insertions(+), 28 deletions(-) (limited to 'src/radeon_exa_render.c') diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index 2213a326..f8f66009 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -937,6 +937,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, CARD32 txenable, colorpitch; CARD32 blendcntl; int pixel_shift; + int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400); ACCEL_PREAMBLE(); TRACE; @@ -976,40 +977,61 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, RADEON_SWITCH_TO_3D(); /* setup the vertex shader */ - BEGIN_ACCEL(26); - OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0); - OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); - OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456); + + if (has_tcl) { + BEGIN_ACCEL(28); + OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0); + OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); + OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456); + } else { + BEGIN_ACCEL(10); + OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 1<<8); + OUT_ACCEL_REG(R300_VAP_CNTL, 0x14045a); + } + OUT_ACCEL_REG(R300_VAP_VTE_CNTL, 0x300); OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x4a014001); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6b01); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0xf688); - OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400); - OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); - - OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0); + + + if (has_tcl) { + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x4a014001); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6b01); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0xf688); + } else { + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x46014001); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6701); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0x3b083b08); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0x3b08); + } + + if (has_tcl) { + OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400); + OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); + + OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0); + + OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); + OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); + OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); + OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); + OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000); + } OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, 0x1); OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (0x2 << 3) | 0x2); - OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); - OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); - OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); - OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); - OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000); FINISH_ACCEL(); - if (IS_R300_VARIANT) { + if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) { /* setup pixel shader */ BEGIN_ACCEL(16); OUT_ACCEL_REG(R300_RS_COUNT, 0x40002); @@ -1030,7 +1052,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); FINISH_ACCEL(); } else { - BEGIN_ACCEL(22); + BEGIN_ACCEL(23); OUT_ACCEL_REG(R300_RS_COUNT, 0x40002); OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); -- cgit v1.2.3