From 8c9b8de0373797cba6f0a27e6b6f461e1070fef9 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 25 Jun 2008 10:28:26 +0200 Subject: radeon: flush & wait for 2d & dma idle after 2d blit This should help to avoid 2d & 3d engine to step on each other dma transaction. --- src/radeon_accelfuncs.c | 40 ++++++++++++++++++++++++++++++++++++++++ src/radeon_exa_funcs.c | 15 +++++++++++++++ src/radeon_reg.h | 1 + 3 files changed, 56 insertions(+) (limited to 'src') diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c index 3c0b8a0f..56793cd0 100644 --- a/src/radeon_accelfuncs.c +++ b/src/radeon_accelfuncs.c @@ -151,6 +151,11 @@ FUNC_NAME(RADEONSetupForSolidFill)(ScrnInfoPtr pScrn, | RADEON_DST_Y_TOP_TO_BOTTOM)); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); } /* Subsequent XAA SolidFillRect @@ -205,6 +210,11 @@ FUNC_NAME(RADEONSetupForSolidLine)(ScrnInfoPtr pScrn, OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); } /* Subsequent XAA solid horizontal and vertical lines */ @@ -324,6 +334,11 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, OUT_ACCEL_REG(RADEON_BRUSH_DATA0, pat); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); } /* Helper function to draw last point for dashed lines */ @@ -358,6 +373,11 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->dash_fg); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); } /* Subsequent XAA dashed line */ @@ -461,6 +481,11 @@ FUNC_NAME(RADEONSetupForScreenToScreenCopy)(ScrnInfoPtr pScrn, (ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0))); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); info->trans_color = trans_color; FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color); @@ -553,6 +578,11 @@ FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn, #endif FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); } /* Subsequent XAA 8x8 pattern color expansion. Because they are used in @@ -1086,6 +1116,11 @@ FUNC_NAME(RADEONSetClippingRectangle)(ScrnInfoPtr pScrn, OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, tmp2); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color); } @@ -1105,6 +1140,11 @@ FUNC_NAME(RADEONDisableClipping)(ScrnInfoPtr pScrn) RADEON_DEFAULT_SC_BOTTOM_MAX)); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color); } diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c index 13a7de50..29f7c36e 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c @@ -116,6 +116,11 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM)); OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); return TRUE; } @@ -169,6 +174,11 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset); OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, src_pitch_offset); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); } static Bool @@ -343,6 +353,11 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, OUT_ACCEL_REG(RADEON_DST_Y_X, (dstY << 16) | dstX); OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); FINISH_ACCEL(); + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + FINISH_ACCEL(); } #endif diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 52795b16..59e2f123 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -1458,6 +1458,7 @@ # define RADEON_RB2D_DC_FLUSH_ALL 0xf # define RADEON_RB2D_DC_BUSY (1 << 31) #define RADEON_RB2D_DSTCACHE_MODE 0x3428 +#define RADEON_DSTCACHE_CTLSTAT 0x1714 #define RADEON_RB3D_ZCACHE_MODE 0x3250 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 -- cgit v1.2.3