1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
|
/*
* Copyright 2005 Eric Anholt
* Copyright 2005 Benjamin Herrenschmidt
* Copyright 2008 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Eric Anholt <anholt@FreeBSD.org>
* Zack Rusin <zrusin@trolltech.com>
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Alex Deucher <alexander.deucher@amd.com>
* Matthias Hopf <mhopf@suse.de>
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "radeon.h"
#ifdef XF86DRI
#include "radeon_drm.h"
#endif
#include "radeon_macros.h"
#include "radeon_probe.h"
#include "radeon_version.h"
#include "radeon_vbo.h"
PixmapPtr
RADEONGetDrawablePixmap(DrawablePtr pDrawable)
{
if (pDrawable->type == DRAWABLE_WINDOW)
return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable);
else
return (PixmapPtr)pDrawable;
}
void RADEONVlineHelperClear(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
accel_state->vline_crtc = NULL;
accel_state->vline_y1 = -1;
accel_state->vline_y2 = 0;
}
void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
accel_state->vline_crtc = radeon_pick_best_crtc(pScrn, x1, x2, y1, y2);
if (accel_state->vline_y1 == -1)
accel_state->vline_y1 = y1;
if (y1 < accel_state->vline_y1)
accel_state->vline_y1 = y1;
if (y2 > accel_state->vline_y2)
accel_state->vline_y2 = y2;
}
Bool RADEONValidPM(uint32_t pm, int bpp)
{
uint8_t r, g, b, a;
Bool ret = FALSE;
switch (bpp) {
case 8:
a = pm & 0xff;
if ((a == 0) || (a == 0xff))
ret = TRUE;
break;
case 16:
r = (pm >> 11) & 0x1f;
g = (pm >> 5) & 0x3f;
b = (pm >> 0) & 0x1f;
if (((r == 0) || (r == 0x1f)) &&
((g == 0) || (g == 0x3f)) &&
((b == 0) || (b == 0x1f)))
ret = TRUE;
break;
case 32:
a = (pm >> 24) & 0xff;
r = (pm >> 16) & 0xff;
g = (pm >> 8) & 0xff;
b = (pm >> 0) & 0xff;
if (((a == 0) || (a == 0xff)) &&
((r == 0) || (r == 0xff)) &&
((g == 0) || (g == 0xff)) &&
((b == 0) || (b == 0xff)))
ret = TRUE;
break;
default:
break;
}
return ret;
}
Bool RADEONCheckBPP(int bpp)
{
switch (bpp) {
case 8:
case 16:
case 32:
return TRUE;
default:
break;
}
return FALSE;
}
static Bool radeon_vb_get(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
accel_state->vb_mc_addr = info->gartLocation + info->dri->bufStart +
(accel_state->ib->idx*accel_state->ib->total)+
(accel_state->ib->total / 2);
accel_state->vb_total = (accel_state->ib->total / 2);
accel_state->vb_ptr = (pointer)((char*)accel_state->ib->address +
(accel_state->ib->total / 2));
accel_state->vb_offset = 0;
return TRUE;
}
void radeon_vb_discard(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
info->accel_state->vb_start_op = -1;
}
int radeon_cp_start(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
#if defined(XF86DRM_MODE)
if (info->cs) {
if (CS_FULL(info->cs)) {
radeon_cs_flush_indirect(pScrn);
}
accel_state->ib_reset_op = info->cs->cdw;
accel_state->vb_start_op = accel_state->vb_offset;
} else
#endif
{
accel_state->ib = RADEONCPGetBuffer(pScrn);
if (!radeon_vb_get(pScrn)) {
return -1;
}
accel_state->vb_start_op = accel_state->vb_offset;
}
return 0;
}
void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
if (info->cs) {
if (accel_state->vb_bo) {
if (accel_state->vb_start_op != accel_state->vb_offset) {
accel_state->finish_op(pScrn, vert_size);
accel_state->ib_reset_op = info->cs->cdw;
}
/* release the current VBO */
radeon_vbo_put(pScrn);
}
/* get a new one */
radeon_vbo_get(pScrn);
return;
}
if (accel_state->vb_start_op != -1) {
accel_state->finish_op(pScrn, vert_size);
radeon_cp_start(pScrn);
}
return;
}
void radeon_ib_discard(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
int ret;
if (info->accel_state->ib_reset_op) {
/* if we have data just reset the CS and ignore the operation */
info->cs->cdw = info->accel_state->ib_reset_op;
info->accel_state->ib_reset_op = 0;
goto out;
}
info->accel_state->vb_offset = 0;
info->accel_state->vb_start_op = -1;
if (CS_FULL(info->cs)) {
radeon_cs_flush_indirect(pScrn);
return;
}
radeon_cs_erase(info->cs);
ret = radeon_cs_space_check_with_bo(info->cs,
info->accel_state->vb_bo,
RADEON_GEM_DOMAIN_GTT, 0);
if (ret)
ErrorF("space check failed in flush\n");
out:
if (info->dri2.enabled) {
info->accel_state->XInited3D = FALSE;
info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
}
}
|
