diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-10-17 11:25:52 +0100 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-10-17 14:02:15 +0100 |
commit | 41be80a8cae1eb0e294392e5033511bfdf2895c5 (patch) | |
tree | c55fbda07248a91a337f98828e5e09715f747582 | |
parent | ba6c82cd9d8089354b90632ca8edbb35cc09b9c4 (diff) |
sna: Enable support for SECURE batch buffers
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r-- | configure.ac | 9 | ||||
-rw-r--r-- | src/sna/kgem.c | 24 | ||||
-rw-r--r-- | src/sna/kgem.h | 4 |
3 files changed, 35 insertions, 2 deletions
diff --git a/configure.ac b/configure.ac index 972d9188..ab3f3d2e 100644 --- a/configure.ac +++ b/configure.ac @@ -292,6 +292,15 @@ if test "x$USERPTR" = xyes; then AC_DEFINE(USE_USERPTR,1,[Assume USERPTR support]) fi +AC_ARG_ENABLE(secure-batches, + AS_HELP_STRING([--enable-secure-batches], + [Enable use of secure batches (experimental) [default=no]]), + [SECURE_BATCHES="$enableval"], + [SECURE_BATCHES=no]) +if test "x$SECURE_BATCHES" = xyes; then + AC_DEFINE(USE_SECURE_BATCHES,1,[Test for kernel support of secure batches]) +fi + AC_ARG_ENABLE(async-swap, AS_HELP_STRING([--enable-async-swap], [Enable use of asynchronous swaps (experimental) [default=no]]), diff --git a/src/sna/kgem.c b/src/sna/kgem.c index 46c898f7..ae76a39d 100644 --- a/src/sna/kgem.c +++ b/src/sna/kgem.c @@ -69,8 +69,14 @@ search_snoop_cache(struct kgem *kgem, unsigned int num_pages, unsigned flags); #define DBG_NO_UPLOAD_ACTIVE 0 #define DBG_NO_MAP_UPLOAD 0 #define DBG_NO_RELAXED_FENCING 0 +#define DBG_NO_SECURE_BATCHES 0 #define DBG_DUMP 0 +#ifndef USE_SECURE_BATCHES +#undef DBG_NO_SECURE_BATCHES +#define DBG_NO_SECURE_BATCHES 1 +#endif + #define SHOW_BATCH 0 /* Worst case seems to be 965gm where we cannot write within a cacheline that @@ -93,7 +99,8 @@ search_snoop_cache(struct kgem *kgem, unsigned int num_pages, unsigned flags); #define IS_USER_MAP(ptr) ((uintptr_t)(ptr) & 2) #define __MAP_TYPE(ptr) ((uintptr_t)(ptr) & 3) -#define LOCAL_I915_PARAM_HAS_SEMAPHORES 20 +#define LOCAL_I915_PARAM_HAS_SEMAPHORES 20 +#define LOCAL_I915_PARAM_HAS_SECURE_BATCHES 23 #define LOCAL_I915_GEM_USERPTR 0x32 #define LOCAL_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + LOCAL_I915_GEM_USERPTR, struct local_i915_gem_userptr) @@ -767,6 +774,14 @@ static bool test_has_userptr(struct kgem *kgem) #endif } +static bool test_has_secure_batches(struct kgem *kgem) +{ + if (DBG_NO_SECURE_BATCHES) + return false; + + return gem_param(kgem, LOCAL_I915_PARAM_HAS_SECURE_BATCHES) > 0; +} + static int kgem_get_screen_index(struct kgem *kgem) { struct sna *sna = container_of(kgem, struct sna, kgem); @@ -822,6 +837,10 @@ void kgem_init(struct kgem *kgem, int fd, struct pci_device *dev, int gen) DBG(("%s: can blt to cpu? %d\n", __FUNCTION__, kgem->can_blt_cpu)); + kgem->has_secure_batches = test_has_secure_batches(kgem); + DBG(("%s: can use privileged batchbuffers? %d\n", __FUNCTION__, + kgem->has_secure_batches)); + if (!is_hw_supported(kgem, dev)) { xf86DrvMsg(kgem_get_screen_index(kgem), X_WARNING, "Detected unsupported/dysfunctional hardware, disabling acceleration.\n"); @@ -2147,6 +2166,7 @@ void kgem_reset(struct kgem *kgem) kgem->nbatch = 0; kgem->surface = kgem->batch_size; kgem->mode = KGEM_NONE; + kgem->batch_flags = 0; kgem->flush = 0; kgem->next_request = __kgem_request_alloc(); @@ -2258,7 +2278,7 @@ void _kgem_submit(struct kgem *kgem) execbuf.num_cliprects = 0; execbuf.DR1 = 0; execbuf.DR4 = 0; - execbuf.flags = kgem->ring; + execbuf.flags = kgem->ring | kgem->batch_flags; execbuf.rsvd1 = 0; execbuf.rsvd2 = 0; diff --git a/src/sna/kgem.h b/src/sna/kgem.h index c8813ebe..276df4fc 100644 --- a/src/sna/kgem.h +++ b/src/sna/kgem.h @@ -138,6 +138,9 @@ struct kgem { int16_t count; } vma[NUM_MAP_TYPES]; + uint32_t batch_flags; +#define I915_EXEC_SECURE (1<<9) + uint16_t nbatch; uint16_t surface; uint16_t nexec; @@ -158,6 +161,7 @@ struct kgem { uint32_t has_relaxed_fencing :1; uint32_t has_relaxed_delta :1; uint32_t has_semaphores :1; + uint32_t has_secure_batches :1; uint32_t has_cacheing :1; uint32_t has_llc :1; |