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authorChris Wilson <chris@chris-wilson.co.uk>2011-07-30 09:00:06 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2011-07-30 09:06:47 +0100
commit6f919264da69ed8bce6f2573629d89962a670783 (patch)
tree8fdb5b7edd35b6154c1b2644a4b4022cb204af8b
parent326a84e832c43cc200a32e091b4e60b8b6a4a7c8 (diff)
sna: Mark the stencil as untiled
In reality, Mesa will be treating it as W-tiling, only we have no way of communicating that requirement to the kernel (as not only does the kernel not understand W-tiling, but also the GTT is incapable of fencing a W-tiled region.). Ported from Chad Versace's 3e55f3e88. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--src/sna/sna_dri.c16
1 files changed, 13 insertions, 3 deletions
diff --git a/src/sna/sna_dri.c b/src/sna/sna_dri.c
index ec656426..9b0ce200 100644
--- a/src/sna/sna_dri.c
+++ b/src/sna/sna_dri.c
@@ -246,12 +246,22 @@ sna_dri_create_buffer(DrawablePtr drawable,
*
* If we neglect to double the pitch, then
* drm_intel_gem_bo_map_gtt() maps the memory incorrectly.
+ *
+ * The alignment for W-tiling is quite different to the
+ * nominal no-tiling case, so we have to account for
+ * the tiled access pattern explicitly.
+ *
+ * The stencil buffer is W tiled. However, we request from
+ * the kernel a non-tiled buffer because the kernel does
+ * not understand W tiling and the GTT is incapable of
+ * W fencing.
*/
bpp = format ? format : drawable->bitsPerPixel;
bo = kgem_create_2d(&sna->kgem,
- drawable->width,
- drawable->height/2, 2*bpp,
- I915_TILING_Y,
+ ALIGN(drawable->width, 64),
+ ALIGN((drawable->height + 1) / 2, 64),
+ 2*bpp,
+ I915_TILING_NONE,
CREATE_EXACT);
break;