partially revert kernel commit

commit b91ad0ec52770dcb622b94fc1f57e076686f427a
Author: Zhenyu Wang <zhenyuw@linux.intel.com>
Date:   Fri Feb 5 09:14:17 2010 +0800

    drm/i915: Rework DPLL calculation parameters for Ironlake

    Got Ironlake DPLL parameter table, which reflects the hardware
    optimized values. So this one trys to list DPLL parameters for
    different output types, should potential fix clock issue seen
    on new Arrandale CPUs.

    This fixes DPLL setting failure on one 1920x1080 dual channel
    LVDS for Ironlake. Test has also been made on LVDS panels with
    smaller size and CRT/HDMI/DP ports for different monitors on
    their all supported modes.

    Update:
    - Change name of double LVDS to dual LVDS.
    - Fix SSC 120M reference clock to use the right range.

    Cc: CSJ <changsijay@gmail.com>
    Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
    Signed-off-by: Eric Anholt <eric@anholt.net>

Since it causes problems on reyk's laptop. Said laptop is still not 100%
awesome, but it is now at least usable.

1 files changed, 36 insertions, 27 deletions

diff --git a/src/i830_display.c b/src/i830_display.c
index bd5bf120..e4fa1505 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -155,10 +155,33 @@ struct intel_limit {
 #define IRONLAKE_DOT_MAX         350000
 #define IRONLAKE_VCO_MIN         1760000
 #define IRONLAKE_VCO_MAX         3510000
+#define IRONLAKE_N_MIN           1
+#define IRONLAKE_N_MAX           6
+#define IRONLAKE_M_MIN           79
+#define IRONLAKE_M_MAX           127
 #define IRONLAKE_M1_MIN          12
 #define IRONLAKE_M1_MAX          22
 #define IRONLAKE_M2_MIN          5
 #define IRONLAKE_M2_MAX          9
+#define IRONLAKE_P_SDVO_DAC_MIN  5
+#define IRONLAKE_P_SDVO_DAC_MAX  80
+#define IRONLAKE_P_LVDS_MIN      28
+#define IRONLAKE_P_LVDS_MAX      112
+#define IRONLAKE_P1_MIN          1
+#define IRONLAKE_P1_MAX          8
+#define IRONLAKE_P2_SDVO_DAC_SLOW 10
+#define IRONLAKE_P2_SDVO_DAC_FAST 5
+#define IRONLAKE_P2_LVDS_SLOW    14 /* single channel */
+#define IRONLAKE_P2_LVDS_FAST    7  /* double channel */
+#define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
+
+#define IRONLAKE_P_DISPLAY_PORT_MIN	10
+#define IRONLAKE_P_DISPLAY_PORT_MAX	20
+#define IRONLAKE_P2_DISPLAY_PORT_FAST	10
+#define IRONLAKE_P2_DISPLAY_PORT_SLOW	10
+#define IRONLAKE_P2_DISPLAY_PORT_LIMIT	0
+#define IRONLAKE_P1_DISPLAY_PORT_MIN	1
+#define IRONLAKE_P1_DISPLAY_PORT_MAX	2
 
 #define INTEL_LIMIT_I8XX_DVO_DAC    0
 #define INTEL_LIMIT_I8XX_LVDS	    1
@@ -479,26 +502,26 @@ static const intel_limit_t intel_limits[] = {
     },
 };
 
-static const intel_limit_t intel_limits_ironlake_dac = {
+static const intel_limit_t intel_limits_ironlake_sdvo = {
     .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
     .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
-    .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
-    .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
+    .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
+    .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
     .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
     .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
-    .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
-    .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
+    .p   = { .min = IRONLAKE_P_LVDS_MIN,       .max = IRONLAKE_P_LVDS_MAX },
+    .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
     .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
-	.p2_slow = IRONLAKE_DAC_P2_SLOW,
-	.p2_fast = IRONLAKE_DAC_P2_FAST },
+	 .p2_slow = IRONLAKE_P2_LVDS_SLOW,
+	 .p2_fast = IRONLAKE_P2_LVDS_FAST },
     .find_pll = intel_igdng_find_best_PLL,
 };
 
-static const intel_limit_t intel_limits_ironlake_single_lvds = {
+static const intel_limit_t intel_limits_ironlake_lvds = {
     .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
     .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
-    .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
-    .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
+    .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
+    .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
     .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
     .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
     .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
@@ -561,25 +584,11 @@ static const intel_limit_t *intel_igdng_limit(xf86CrtcPtr crtc)
     intel_screen_private *intel = intel_get_screen_private(scrn);
     const intel_limit_t *limit;
 
+    /* XXX displayport */
     if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
-	int refclk = 120;
-
-	if (intel->lvds_use_ssc && intel->lvds_ssc_freq)
-	    refclk = 100;
-
-	if ((INREG(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) {
-	    if (refclk == 100)
-		limit = &intel_limits_ironlake_dual_lvds_100m;
-	    else
-		limit = &intel_limits_ironlake_dual_lvds;
-	} else {
-	    if (refclk == 100)
-		limit = &intel_limits_ironlake_single_lvds_100m;
-	    else
-		limit = &intel_limits_ironlake_single_lvds;
-	}
+	limit = &intel_limits_ironlake_lvds;
     } else
-	limit = &intel_limits_ironlake_dac;
+	limit = &intel_limits_ironlake_sdvo;
 
     return limit;
 }