Revert 4deb8a793907015dbf821d2e343d9527a5ae2512 plus a one liner

Change the error bounds on the pll search, since it is *far* too tight for
some things. This commit didn't hit the linux kernel yet, but adam jackson's
commit message on the patch sent to intel-gfx was:

From: Adam Jackson <ajax@redhat.com>
Subject: [Intel-gfx] [PATCH] drm/i915: Make G4X-style PLL search more
permissive
To: intel-gfx@lists.freedesktop.org

Fixes an Ironlake laptop with a 68.940MHz 1280x800 panel and 120MHz SSC
reference clock.

More generally, the 0.488% tolerance used before is just too tight to
reliably find a PLL setting.  I extracted the search algorithm and
modified it to find the dot clocks with maximum error over the valid
range for the given output type:

http://people.freedesktop.org/~ajax/intel_g4x_find_best_pll.c

This gave:

Worst dotclock for Ironlake DAC refclk is 350000kHz (error 0.00571)
Worst dotclock for Ironlake SL-LVDS refclk is 102321kHz (error 0.00524)
Worst dotclock for Ironlake DL-LVDS refclk is 219642kHz (error 0.00488)
Worst dotclock for Ironlake SL-LVDS SSC refclk is 84374kHz (error
0.00529)
Worst dotclock for Ironlake DL-LVDS SSC refclk is 183035kHz (error
0.00488)
Worst dotclock for G4X SDVO refclk is 50000kHz (error 0.17332)
Worst dotclock for G4X HDMI refclk is 334400kHz (error 0.00478)
Worst dotclock for G4X SL-LVDS refclk is 95571kHz (error 0.00449)
Worst dotclock for G4X DL-LVDS refclk is 224000kHz (error 0.00510)

The SDVO number looks a bit suspicious, which I haven't tracked down
yet.  But it's clear that the old threshold is too tight.

Signed-off-by: Adam Jackson <ajax@redhat.com>

still fixes reyk's x201 and doesn't fuck multihead on mine (which the
previous patch did).

Signed-off-by: Owain G. Ainsworth <oga@openbsd.org>

1 files changed, 29 insertions, 37 deletions

diff --git a/src/i830_display.c b/src/i830_display.c
index e4fa1505..c96b9d6e 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -155,33 +155,10 @@ struct intel_limit {
 #define IRONLAKE_DOT_MAX         350000
 #define IRONLAKE_VCO_MIN         1760000
 #define IRONLAKE_VCO_MAX         3510000
-#define IRONLAKE_N_MIN           1
-#define IRONLAKE_N_MAX           6
-#define IRONLAKE_M_MIN           79
-#define IRONLAKE_M_MAX           127
 #define IRONLAKE_M1_MIN          12
 #define IRONLAKE_M1_MAX          22
 #define IRONLAKE_M2_MIN          5
 #define IRONLAKE_M2_MAX          9
-#define IRONLAKE_P_SDVO_DAC_MIN  5
-#define IRONLAKE_P_SDVO_DAC_MAX  80
-#define IRONLAKE_P_LVDS_MIN      28
-#define IRONLAKE_P_LVDS_MAX      112
-#define IRONLAKE_P1_MIN          1
-#define IRONLAKE_P1_MAX          8
-#define IRONLAKE_P2_SDVO_DAC_SLOW 10
-#define IRONLAKE_P2_SDVO_DAC_FAST 5
-#define IRONLAKE_P2_LVDS_SLOW    14 /* single channel */
-#define IRONLAKE_P2_LVDS_FAST    7  /* double channel */
-#define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
-
-#define IRONLAKE_P_DISPLAY_PORT_MIN	10
-#define IRONLAKE_P_DISPLAY_PORT_MAX	20
-#define IRONLAKE_P2_DISPLAY_PORT_FAST	10
-#define IRONLAKE_P2_DISPLAY_PORT_SLOW	10
-#define IRONLAKE_P2_DISPLAY_PORT_LIMIT	0
-#define IRONLAKE_P1_DISPLAY_PORT_MIN	1
-#define IRONLAKE_P1_DISPLAY_PORT_MAX	2
 
 #define INTEL_LIMIT_I8XX_DVO_DAC    0
 #define INTEL_LIMIT_I8XX_LVDS	    1
@@ -502,26 +479,26 @@ static const intel_limit_t intel_limits[] = {
     },
 };
 
-static const intel_limit_t intel_limits_ironlake_sdvo = {
+static const intel_limit_t intel_limits_ironlake_dac = {
     .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
     .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
-    .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
-    .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
+    .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
+    .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
     .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
     .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
-    .p   = { .min = IRONLAKE_P_LVDS_MIN,       .max = IRONLAKE_P_LVDS_MAX },
-    .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
+    .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
+    .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
     .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
-	 .p2_slow = IRONLAKE_P2_LVDS_SLOW,
-	 .p2_fast = IRONLAKE_P2_LVDS_FAST },
+	.p2_slow = IRONLAKE_DAC_P2_SLOW,
+	.p2_fast = IRONLAKE_DAC_P2_FAST },
     .find_pll = intel_igdng_find_best_PLL,
 };
 
-static const intel_limit_t intel_limits_ironlake_lvds = {
+static const intel_limit_t intel_limits_ironlake_single_lvds = {
     .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
     .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
-    .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
-    .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
+    .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
+    .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
     .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
     .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
     .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
@@ -584,11 +561,25 @@ static const intel_limit_t *intel_igdng_limit(xf86CrtcPtr crtc)
     intel_screen_private *intel = intel_get_screen_private(scrn);
     const intel_limit_t *limit;
 
-    /* XXX displayport */
     if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
-	limit = &intel_limits_ironlake_lvds;
+	int refclk = 120;
+
+	if (intel->lvds_use_ssc && intel->lvds_ssc_freq)
+	    refclk = 100;
+
+	if ((INREG(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) {
+	    if (refclk == 100)
+		limit = &intel_limits_ironlake_dual_lvds_100m;
+	    else
+		limit = &intel_limits_ironlake_dual_lvds;
+	} else {
+	    if (refclk == 100)
+		limit = &intel_limits_ironlake_single_lvds_100m;
+	    else
+		limit = &intel_limits_ironlake_single_lvds;
+	}
     } else
-	limit = &intel_limits_ironlake_sdvo;
+	limit = &intel_limits_ironlake_dac;
 
     return limit;
 }
@@ -710,7 +701,8 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, xf86CrtcPtr crtc,
     intel_clock_t clock;
     int max_n;
     Bool found = FALSE;
-    int err_most = (target >> 8) + (target >> 10);
+    /* Approximately equals target * 0.00585 */
+    int err_most = (target >> 8) + (target >> 9);
 
     if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
 	if ((INREG(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)