diff options
| author | Edward Sheldrake <ejsheldrake@gmail.com> | 2014-02-03 09:34:33 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2014-02-03 10:04:15 +0000 |
| commit | 1cbc59a917e7352fc68aa0e26b1575cbd0ceab0d (patch) | |
| tree | d0d2aabad9ae331f620968a07198003836825b6d | |
| parent | 7f08250a8960f90f6bd34de8c4a17870703bfa60 (diff) | |
sna/gen4,5: Fix setting pipe control cache flush bits
Cache flush bits are on dword 0, not 1, on gen4 and gen5. Also texture
cache invalidate is only available from Cantiga onwards.
| -rw-r--r-- | src/sna/gen4_render.c | 17 | ||||
| -rw-r--r-- | src/sna/gen4_render.h | 2 | ||||
| -rw-r--r-- | src/sna/gen5_render.c | 6 |
3 files changed, 14 insertions, 11 deletions
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c index 1d164b6e..1580707c 100644 --- a/src/sna/gen4_render.c +++ b/src/sna/gen4_render.c @@ -575,8 +575,10 @@ inline static void gen4_emit_pipe_flush(struct sna *sna) { #if 1 - OUT_BATCH(GEN4_PIPE_CONTROL | (4 - 2)); - OUT_BATCH(GEN4_PIPE_CONTROL_WC_FLUSH); + OUT_BATCH(GEN4_PIPE_CONTROL | + GEN4_PIPE_CONTROL_WC_FLUSH | + (4 - 2)); + OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); #else @@ -600,14 +602,13 @@ gen4_emit_pipe_break(struct sna *sna) inline static void gen4_emit_pipe_invalidate(struct sna *sna) { -#if 0 - OUT_BATCH(GEN4_PIPE_CONTROL | (4 - 2)); - OUT_BATCH(GEN4_PIPE_CONTROL_WC_FLUSH | GEN4_PIPE_CONTROL_TC_FLUSH); + OUT_BATCH(GEN4_PIPE_CONTROL | + GEN4_PIPE_CONTROL_WC_FLUSH | + (sna->kgem.gen >= 045 ? GEN4_PIPE_CONTROL_TC_FLUSH : 0) | + (4 - 2)); + OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); -#else - OUT_BATCH(MI_FLUSH); -#endif } static void gen4_emit_primitive(struct sna *sna) diff --git a/src/sna/gen4_render.h b/src/sna/gen4_render.h index 53c7fc2f..64d11e66 100644 --- a/src/sna/gen4_render.h +++ b/src/sna/gen4_render.h @@ -112,7 +112,7 @@ #define GEN4_PIPE_CONTROL_DEPTH_STALL (1 << 13) #define GEN4_PIPE_CONTROL_WC_FLUSH (1 << 12) #define GEN4_PIPE_CONTROL_IS_FLUSH (1 << 11) -#define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10) +#define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10) /* ctg+ */ #define GEN4_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) #define GEN4_PIPE_CONTROL_GLOBAL_GTT (1 << 2) #define GEN4_PIPE_CONTROL_LOCAL_PGTT (0 << 2) diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c index 8fb47cb6..25555e0e 100644 --- a/src/sna/gen5_render.c +++ b/src/sna/gen5_render.c @@ -1016,8 +1016,10 @@ inline static void gen5_emit_pipe_flush(struct sna *sna) { #if 0 - OUT_BATCH(GEN5_PIPE_CONTROL | (4 - 2)); - OUT_BATCH(GEN5_PIPE_CONTROL_WC_FLUSH); + OUT_BATCH(GEN5_PIPE_CONTROL | + GEN5_PIPE_CONTROL_WC_FLUSH | + (4 - 2)); + OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); #else |