diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-07-06 09:42:37 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-07-06 10:06:16 +0100 |
| commit | 5784e0f21dc91f33c99a507105a0695cc53d6574 (patch) | |
| tree | 3b4a4d1823166a57e8a88a537eb5ee097398bf16 | |
| parent | 1ee10cc3b2aa0888753eeb25c7fde7296a3c92eb (diff) | |
Allow matching against any device supported by drm/i915
However we cannot enable acceleration if we do not recognise its
hardware layout or instruction set.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| -rw-r--r-- | src/intel_driver.c | 3 | ||||
| -rw-r--r-- | src/intel_module.c | 18 | ||||
| -rw-r--r-- | src/sna/kgem.c | 5 |
3 files changed, 20 insertions, 6 deletions
diff --git a/src/intel_driver.c b/src/intel_driver.c index 77611f53..f2770d6c 100644 --- a/src/intel_driver.c +++ b/src/intel_driver.c @@ -417,6 +417,9 @@ static Bool has_relaxed_fencing(struct intel_screen_private *intel) static Bool can_accelerate_blt(struct intel_screen_private *intel) { + if (INTEL_INFO(intel)->gen == 0) + return FALSE; + if (0 && (IS_I830(intel) || IS_845G(intel))) { /* These pair of i8xx chipsets have a crippling erratum * that prevents the use of a PTE entry by the BLT diff --git a/src/intel_module.c b/src/intel_module.c index af82cff4..f8ba1494 100644 --- a/src/intel_module.c +++ b/src/intel_module.c @@ -48,6 +48,10 @@ static struct intel_device_info *chipset_info; +static const struct intel_device_info intel_generic_info = { + .gen = 0, +}; + static const struct intel_device_info intel_i81x_info = { .gen = 10, }; @@ -215,6 +219,7 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ), + INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), { 0, 0, 0 }, }; @@ -225,6 +230,7 @@ void intel_detect_chipset(ScrnInfoPtr scrn, int i; chipset->info = chipset_info; + chipset->name = NULL; for (i = 0; intel_chipsets[i].name != NULL; i++) { if (DEVICE_ID(pci) == intel_chipsets[i].token) { @@ -232,12 +238,14 @@ void intel_detect_chipset(ScrnInfoPtr scrn, break; } } - if (intel_chipsets[i].name == NULL) { - chipset->name = "unknown chipset"; + if (chipset->name == NULL) { + xf86DrvMsg(scrn->scrnIndex, X_WARNING, "unknown chipset\n"); + chipset->name = "unknown"; + } else { + xf86DrvMsg(scrn->scrnIndex, X_INFO, + "Integrated Graphics Chipset: Intel(R) %s\n", + chipset->name); } - - xf86DrvMsg(scrn->scrnIndex, X_INFO, - "Integrated Graphics Chipset: Intel(R) %s\n", chipset->name); } /* diff --git a/src/sna/kgem.c b/src/sna/kgem.c index abae21a6..2ace6ca5 100644 --- a/src/sna/kgem.c +++ b/src/sna/kgem.c @@ -543,7 +543,10 @@ static struct list *active(struct kgem *kgem, int num_pages, int tiling) static size_t agp_aperture_size(struct pci_device *dev, int gen) { - return dev->regions[gen < 30 ? 0 : 2].size; + /* XXX assume that only future chipsets are unknown and follow + * the post gen2 PCI layout. + */ + return dev->regions[(gen && gen < 30) ? 0 : 2].size; } static size_t |