diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2013-03-01 23:46:07 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2013-03-01 23:47:01 +0000 |
| commit | ae3531c3a1d72a73b25c5563b4db029f051262cb (patch) | |
| tree | 2368de376604291dd50341aeecb94727e9d65c33 | |
| parent | fef6cdae9ebd217843bab2f65c87b59f8a9f782e (diff) | |
Fix Haswell CRW PCI-IDs
As we missed the PCI-ID for the CRW GT1 variant, we would not have enabled
render support for those particular Haswell machines.
Reported-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | src/intel_driver.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index c98025ba..0dda5b1f 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -219,15 +219,15 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12 -#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22 -#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 +#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 +#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 |