jcs's wip sandybridge diff with the stolen memory calculation from me.

This doesn't have the correct ifing to deal with ironlake yet, also vt switch
does not work.

5 files changed, 310 insertions, 50 deletions

diff --git a/src/i830_crt.c b/src/i830_crt.c
index 8cc061a2..2b6c6572 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -180,12 +180,21 @@ static Bool intel_igdng_crt_detect_hotplug(xf86OutputPtr output)
 {
     ScrnInfoPtr			scrn = output->scrn;
     intel_screen_private	*intel = intel_get_screen_private(scrn);
-    uint32_t adpa;
+    uint32_t adpa, temp;
     Bool ret;
 
-    adpa = INREG(PCH_ADPA);
-
-    adpa &= ~ADPA_CRT_HOTPLUG_MASK;
+    temp = adpa = INREG(PCH_ADPA);
+
+    if (1) { // XXX HAS_PCH_CPT(dev)
+	/* Disable DAC before force detect */
+	OUTREG(PCH_ADPA, adpa & ~ADPA_DAC_ENABLE);
+	INREG(PCH_ADPA);
+    } else {
+	adpa &= ~ADPA_CRT_HOTPLUG_MASK;
+	/* disable HPD first */
+	OUTREG(PCH_ADPA, adpa);
+	INREG(PCH_ADPA);
+    }
 
     adpa |= (ADPA_CRT_HOTPLUG_PERIOD_64 |
 	     ADPA_CRT_HOTPLUG_WARMUP_5MS |
@@ -203,6 +212,11 @@ static Bool intel_igdng_crt_detect_hotplug(xf86OutputPtr output)
     while (INREG(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
       ;
 
+    if (1) { // XXX HAS_PCH_CPT 
+	OUTREG(PCH_ADPA, temp);
+	INREG(PCH_ADPA);
+    }
+
     /* Check the status to see if both blue and green are on now */
     adpa = INREG(PCH_ADPA) & ADPA_CRT_HOTPLUG_MONITOR_MASK;
     if (adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR ||
diff --git a/src/i830_display.c b/src/i830_display.c
index febcf5a4..dd26d8f0 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1367,6 +1367,124 @@ static void ironlake_fdi_link_train(xf86CrtcPtr crtc)
     ErrorF("FDI train done\n");
 }
 
+static const int snb_b_fdi_train_param [] = {
+        FDI_LINK_TRAIN_400MV_0DB_SNB_B,
+        FDI_LINK_TRAIN_400MV_6DB_SNB_B,
+        FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
+        FDI_LINK_TRAIN_800MV_0DB_SNB_B,
+};
+
+static void gen6_fdi_link_train(xf86CrtcPtr crtc)
+{
+    ScrnInfoPtr scrn = crtc->scrn;
+    intel_screen_private *intel = intel_get_screen_private(scrn);
+    I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+    int pipe = intel_crtc->pipe;
+    int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
+    int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
+    int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
+    int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
+    uint32_t temp, i = 0;
+    
+    /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
+       for train result */
+    temp = INREG(fdi_rx_imr_reg);
+    temp &= ~FDI_RX_SYMBOL_LOCK;
+    temp &= ~FDI_RX_BIT_LOCK;
+    OUTREG(fdi_rx_imr_reg, temp);
+    INREG(fdi_rx_imr_reg);
+    usleep(150);
+
+    /* enable CPU FDI TX and PCH FDI RX */
+    temp = INREG(fdi_tx_reg);
+    temp |= FDI_TX_ENABLE;
+    temp &= ~(7 << 19);
+    temp |= /*(intel_crtc->fdi_lanes - 1)*/3 << 19;
+    temp &= ~FDI_LINK_TRAIN_NONE;
+    temp |= FDI_LINK_TRAIN_PATTERN_1;
+    temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+    /* SNB-B */
+    temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+    OUTREG(fdi_tx_reg, temp);
+    INREG(fdi_tx_reg);
+    
+    temp = INREG(fdi_rx_reg);
+    if (1) { // XXX HAS_PCH_CPT(dev)) {
+        temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+        temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+    } else {
+        temp &= ~FDI_LINK_TRAIN_NONE;
+        temp |= FDI_LINK_TRAIN_PATTERN_1;
+    }
+    OUTREG(fdi_rx_reg, temp | FDI_RX_ENABLE);
+    INREG(fdi_rx_reg);
+    usleep(150);
+    
+    for (i = 0; i < 4; i++) {
+        temp = INREG(fdi_tx_reg);
+        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+        temp |= snb_b_fdi_train_param[i];
+        OUTREG(fdi_tx_reg, temp);
+        INREG(fdi_tx_reg);
+	
+        temp = INREG(fdi_rx_iir_reg);
+	ErrorF("FDI_RX_IIR 0x%x\n", temp);
+
+	if ((temp & FDI_RX_BIT_LOCK)) {
+	    ErrorF("FDI train 1 done.\n");
+	    OUTREG(fdi_rx_iir_reg,
+		       temp | FDI_RX_BIT_LOCK);
+	    break;
+	}
+    }
+    if (i == 4)
+	ErrorF("FDI train 1 fail!\n");
+
+    /* Train 2 */
+    temp = INREG(fdi_tx_reg);
+    temp &= ~FDI_LINK_TRAIN_NONE;
+    temp |= FDI_LINK_TRAIN_PATTERN_2;
+    if (IS_GEN6(intel)) {
+	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+	/* SNB-B */
+	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+    }
+    OUTREG(fdi_tx_reg, temp);
+
+    temp = INREG(fdi_rx_reg);
+    if (1) { // XXX HAS_PCH_CPT(dev)) {
+	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
+    } else {
+	temp &= ~FDI_LINK_TRAIN_NONE;
+	temp |= FDI_LINK_TRAIN_PATTERN_2;
+    }
+    OUTREG(fdi_rx_reg, temp);
+    usleep(150);
+
+    for (i = 0; i < 4; i++) {
+        temp = INREG(fdi_tx_reg);
+        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+        temp |= snb_b_fdi_train_param[i];
+        OUTREG(fdi_tx_reg, temp);
+        INREG(fdi_tx_reg);
+	
+        temp = INREG(fdi_rx_iir_reg);
+	ErrorF("FDI_RX_IIR 0x%x\n", temp);
+
+	if ((temp & FDI_RX_SYMBOL_LOCK)) {
+	    ErrorF("FDI train 2 done.\n");
+	    OUTREG(fdi_rx_iir_reg,
+		       temp | FDI_RX_SYMBOL_LOCK);
+	    break;
+	}
+    }
+    if (i == 4)
+   	ErrorF("FDI train 2 fail!\n");
+
+    ErrorF("FDI train done\n");
+}
+
 static void
 ironlake_crtc_enable(xf86CrtcPtr crtc)
 {
@@ -1404,7 +1522,10 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 
 	/* XXX no LVDS port force */
 	if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
+	    ErrorF("LVDS port force on\n");
 	    temp = INREG(PCH_LVDS);
+	    OUTREG(PCH_LVDS, temp | LVDS_PORT_EN);
+	    INREG(PCH_LVDS);
 	    if ((temp & LVDS_PORT_EN) == 0) {
 		OUTREG(PCH_LVDS, temp | LVDS_PORT_EN);
 		INREG(PCH_LVDS);
@@ -1422,6 +1543,7 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 	INREG(fdi_rx_reg);
 	usleep(200);
 
+	/* Switch from Rawclk to PCDclk */
 	temp = INREG(fdi_rx_reg);
 	OUTREG(fdi_rx_reg, temp | FDI_SEL_PCDCLK); 
 	temp = INREG(fdi_rx_reg);
@@ -1435,8 +1557,10 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 	    usleep(100);
 	}
 
+	i830WaitForVblank(scrn);
 
 
+	/* Enable panel fitting for LVDS */
 #define PF_FILTER_MASK		(3<<23)
 #define PF_FILTER_MED_3x3	(1<<23)
 	if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
@@ -1471,7 +1595,10 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 	OUTREG(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
 
 	/* Train FDI. */
-	ironlake_fdi_link_train(crtc);
+	if (IS_GEN6(intel))
+		gen6_fdi_link_train(crtc);
+	else
+		ironlake_fdi_link_train(crtc);
 
 	/* enable PCH DPLL */
 	temp = INREG(pch_dpll_reg);
@@ -1481,6 +1608,16 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 	}
 	usleep(200);
 
+	if (1) { // XXX HAS_PCH_CPT
+		/* Be sure PCH DPLL SEL is set */
+		temp = INREG(PCH_DPLL_SEL);
+		if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
+			temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
+		else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
+			temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
+		OUTREG(PCH_DPLL_SEL, temp);
+	}
+
 	/* set transcoder timing */
 	OUTREG(trans_htot_reg, INREG(cpu_htot_reg));
 	OUTREG(trans_hblank_reg, INREG(cpu_hblank_reg));
@@ -1490,7 +1627,7 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 	OUTREG(trans_vblank_reg, INREG(cpu_vblank_reg));
 	OUTREG(trans_vsync_reg, INREG(cpu_vsync_reg));
 
-	/* enable normal */
+	/* enable normal train */
 
 	ErrorF("FDI TX link normal\n");
 	temp = INREG(fdi_tx_reg);
@@ -1500,15 +1637,18 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 	INREG(fdi_tx_reg);
 
 	temp = INREG(fdi_rx_reg);
-	temp &= ~FDI_LINK_TRAIN_NONE;
-	temp |= FDI_LINK_TRAIN_NONE;
-	
-	OUTREG(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE);
+        if (1) { //HAS_PCH_CPT(dev)) {
+                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+                temp |= FDI_LINK_TRAIN_NORMAL_CPT;
+        } else {
+                temp &= ~FDI_LINK_TRAIN_NONE;
+                temp |= FDI_LINK_TRAIN_NONE;
+        }
+	OUTREG(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
 	INREG(fdi_rx_reg);
 
 	usleep(100);
 
-	ErrorF("transcoder enable\n");
 	/* enable transcoder */
 	temp = INREG(transconf_reg);
 	temp &= ~PIPE_BPC_MASK;
@@ -1519,7 +1659,6 @@ ironlake_crtc_enable(xf86CrtcPtr crtc)
 	while ((INREG(transconf_reg) & TRANS_STATE_ENABLE) == 0)
 	    ;
 
-	ErrorF("LUT load\n");
 	i830_crtc_load_lut(crtc);
 
 	ErrorF("DPMS on done\n");
@@ -1618,15 +1757,20 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
 
 	ErrorF("FDI RX train 1 preload\n");
 	temp = INREG(fdi_rx_reg);
-	temp &= ~FDI_LINK_TRAIN_NONE;
-	temp |= FDI_LINK_TRAIN_PATTERN_1;
+	if (1) { // XXX HAS_PCH_CPT(dev)
+		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+	} else {
+		temp &= ~FDI_LINK_TRAIN_NONE;
+		temp |= FDI_LINK_TRAIN_PATTERN_1;
+	}
 	OUTREG(fdi_rx_reg, temp);
 	INREG(fdi_rx_reg);
 
 	usleep(100);
 
-	ErrorF("LVDS port force off\n");
 	if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
+	    ErrorF("LVDS port force off\n");
 	    while ((temp = INREG(PCH_LVDS)) & PORT_ENABLE) {
 		OUTREG(PCH_LVDS, temp & ~LVDS_PORT_EN);
 		INREG(PCH_LVDS);
@@ -1661,13 +1805,16 @@ ironlake_crtc_disable(xf86CrtcPtr crtc)
 	INREG(transconf_reg);
 	usleep(100);
 
-	ErrorF("PCH DPLL disable\n");
-	/* disable PCH DPLL */
-	temp = INREG(pch_dpll_reg);
-	OUTREG(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
-	INREG(pch_dpll_reg);
+	if (1) { // XXX HAS_PCH_CPT(dev)
+		ErrorF("PCH DPLL disable\n");
+		/* disable PCH DPLL */
+		temp = INREG(pch_dpll_reg);
+		OUTREG(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
+		INREG(pch_dpll_reg);
+	}
 
 	ErrorF("FDI RX PLL PCD disable\n");
+	/* Switch from PCDclk to Rawclk */
 	temp = INREG(fdi_rx_reg);
 	temp &= ~FDI_SEL_PCDCLK;
 	OUTREG(fdi_rx_reg, temp);
@@ -2384,10 +2531,18 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 
 	lvds = INREG(lvds_reg);
 	lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
-	if (IS_IGDNG(intel))
-	    lvds |= (pipe == 1) ? LVDS_PIPEB_SELECT : 0; 
-	else
-	    lvds |= LVDS_PIPEB_SELECT;
+	if (pipe == 1) {
+	    if (IS_IGDNG(intel))
+		lvds |= PORT_TRANS_B_SEL_CPT;
+	    else
+		lvds |= LVDS_PIPEB_SELECT;
+	} else {
+	    if (IS_IGDNG(intel))
+		lvds &= ~PORT_TRANS_SEL_MASK;
+	    else
+	    	lvds &= ~LVDS_PIPEB_SELECT;
+	}
+
 	/* Set the B0-B3 data pairs corresponding to whether we're going to
 	 * set the DPLLs for dual-channel mode or not.
 	 */
@@ -2427,6 +2582,21 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 	POSTING_READ(lvds_reg);
     }
 
+    if (IS_IGDNG(intel)) {
+	    /* For non-DP output, clear any trans DP clock recovery setting.*/
+	    if (pipe == 0) {
+		    OUTREG(TRANSA_DATA_M1, 0);
+		    OUTREG(TRANSA_DATA_N1, 0);
+		    OUTREG(TRANSA_DP_LINK_M1, 0);
+		    OUTREG(TRANSA_DP_LINK_N1, 0);
+	    } else {
+		    OUTREG(TRANSB_DATA_M1, 0);
+		    OUTREG(TRANSB_DATA_N1, 0);
+		    OUTREG(TRANSB_DP_LINK_M1, 0);
+		    OUTREG(TRANSB_DP_LINK_N1, 0);
+	    }
+    }
+
     OUTREG(fp_reg, fp);
 /*    OUTREG(fp_reg + 4, fp); RHEL had this... wtf? */
     OUTREG(dpll_reg, dpll);
@@ -2497,7 +2667,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
     POSTING_READ(pipeconf_reg);
     i830WaitForVblank(scrn);
 
-    if (IS_IGDNG(intel)) {
+    if (IS_IGDNG(intel) && !IS_GEN6(intel)) {
 	/* enable address swizzle for tiling buffer */
 	temp = INREG(DISP_ARB_CTL);
 	OUTREG(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
diff --git a/src/i830_reg.h b/src/i830_reg.h
index fa4d288c..c0ee9b65 100644
--- a/src/i830_reg.h
+++ b/src/i830_reg.h
@@ -3773,6 +3773,14 @@ typedef enum {
 #define DISPLAY_PORT_PLL_BIOS_1		0x46010
 #define DISPLAY_PORT_PLL_BIOS_2		0x46014
 
+#define PCH_DSPCLK_GATE_D      0x42020
+#define DPFDUNIT_CLOCK_GATE_DISABLE           (1 << 7)
+#define DPARBUNIT_CLOCK_GATE_DISABLE          (1 << 5)
+
+#define PCH_3DCGDIS0           0x46020
+#define MARIUNIT_CLOCK_GATE_DISABLE           (1 << 18)
+#define SVSMUNIT_CLOCK_GATE_DISABLE           (1 << 1)
+
 #define FDI_PLL_FREQ_CTL	0x46030
 #define  FDI_PLL_FREQ_CHANGE_REQUEST	(1<<24)
 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK	0xfff00
@@ -3900,6 +3908,11 @@ typedef enum {
 #define SDE_PORTC_HOTPLUG	(1 << 9)
 #define SDE_PORTB_HOTPLUG	(1 << 8)
 #define SDE_SDVOB_HOTPLUG	(1 << 6)
+/* CPT */
+#define SDE_CRT_HOTPLUG_CPT    (1 << 19)
+#define SDE_PORTD_HOTPLUG_CPT  (1 << 23)
+#define SDE_PORTC_HOTPLUG_CPT  (1 << 22)
+#define SDE_PORTB_HOTPLUG_CPT  (1 << 21)
 
 #define SDEISR	0xc4000
 #define SDEIMR	0xc4004
@@ -3989,6 +4002,17 @@ typedef enum {
 #define PCH_SSC4_PARMS		0xc6210
 #define PCH_SSC4_AUX_PARMS	0xc6214
 
+#define PCH_DPLL_SEL            0xc7000
+#define  TRANSA_DPLL_ENABLE     (1<<3)
+#define  TRANSA_DPLLB_SEL       (1<<0)
+#define  TRANSA_DPLLA_SEL       0
+#define  TRANSB_DPLL_ENABLE     (1<<7)
+#define  TRANSB_DPLLB_SEL       (1<<4)
+#define  TRANSB_DPLLA_SEL       (0)
+#define  TRANSC_DPLL_ENABLE     (1<<11)
+#define  TRANSC_DPLLB_SEL       (1<<8)
+#define  TRANSC_DPLLA_SEL       (0)
+
 /* transcoder */
 
 #define TRANS_HTOTAL_A		0xe0000
@@ -4054,6 +4078,12 @@ typedef enum {
 #define  TRANS_6BPC		(2<<5)
 #define  TRANS_12BPC		(3<<5)
 
+/* CPT */
+#define  PORT_TRANS_A_SEL_CPT   0
+#define  PORT_TRANS_B_SEL_CPT   (1<<29)
+#define  PORT_TRANS_C_SEL_CPT   (2<<29)
+#define  PORT_TRANS_SEL_MASK    (3<<29)
+
 #define FDI_RXA_CHICKEN		0xc200c
 #define FDI_RXB_CHICKEN		0xc2010
 #define  FDI_RX_PHASE_SYNC_POINTER_ENABLE	(1)
@@ -4075,6 +4105,20 @@ typedef enum {
 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X	  (2<<22)
 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X	  (3<<22)
+/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
+   SNB has different settings. */
+
+/* SNB A-stepping */
+#define  FDI_LINK_TRAIN_400MV_0DB_SNB_A         (0x38<<22)
+#define  FDI_LINK_TRAIN_400MV_6DB_SNB_A         (0x02<<22)
+#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01<<22)
+#define  FDI_LINK_TRAIN_800MV_0DB_SNB_A         (0x0<<22)
+/* SNB B-stepping */
+#define  FDI_LINK_TRAIN_400MV_0DB_SNB_B         (0x0<<22)
+#define  FDI_LINK_TRAIN_400MV_6DB_SNB_B         (0x3a<<22)
+#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B       (0x39<<22)
+#define  FDI_LINK_TRAIN_800MV_0DB_SNB_B         (0x38<<22)
+#define  FDI_LINK_TRAIN_VOL_EMP_MASK            (0x3f<<22)
 #define  FDI_DP_PORT_WIDTH_X1		(0<<19)
 #define  FDI_DP_PORT_WIDTH_X2		(1<<19)
 #define  FDI_DP_PORT_WIDTH_X3		(2<<19)
@@ -4109,6 +4153,13 @@ typedef enum {
 #define  FDI_RX_ENHANCE_FRAME_ENABLE	(1<<6)
 #define  FDI_SEL_RAWCLK			(0<<4)
 #define  FDI_SEL_PCDCLK			(1<<4)
+/* CPT */
+#define  FDI_AUTO_TRAINING                      (1<<10)
+#define  FDI_LINK_TRAIN_PATTERN_1_CPT           (0<<8)
+#define  FDI_LINK_TRAIN_PATTERN_2_CPT           (1<<8)
+#define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT        (2<<8)
+#define  FDI_LINK_TRAIN_NORMAL_CPT              (3<<8)
+#define  FDI_LINK_TRAIN_PATTERN_MASK_CPT        (3<<8)
 
 #define FDI_RXA_MISC		0xf0010
 #define FDI_RXB_MISC		0xf1010
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 5d9980eb..4b56f095 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -576,11 +576,16 @@ static void I830SetupOutputs(ScrnInfoPtr scrn)
 	Bool	    lvds_detected = FALSE;
 
 	/* everyone has at least a single analog output */
+	xf86DrvMsg(scrn->scrnIndex, X_WARNING, "doing crt_init\n");
 	i830_crt_init(scrn);
 
+	xf86DrvMsg(scrn->scrnIndex, X_WARNING, "checking for integrated lvds\n");
+
 	/* Set up integrated LVDS */
-	if (IS_MOBILE(intel) && !IS_I830(intel))
-	i830_lvds_init(scrn);
+	if (IS_MOBILE(intel) && !IS_I830(intel)) {
+		xf86DrvMsg(scrn->scrnIndex, X_WARNING, "about to lvds_init\n");
+		i830_lvds_init(scrn);
+	}
 
 	if (IS_IGDNG(intel)) {
 		int found;
@@ -654,7 +659,22 @@ static void i830_init_clock_gating(ScrnInfoPtr scrn)
 
     /* Disable clock gating reported to work incorrectly according to the specs.
      */
-	if (IS_G4X(intel)) {
+	if (IS_IGDNG(intel)) {
+		uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+		if (0 /*XXX IS_IRONLAKE(dev) */) {
+			/* Required for FBC */
+			dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
+			/* Required for CxSR */
+			dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
+
+			OUTREG(PCH_3DCGDIS0,
+					MARIUNIT_CLOCK_GATE_DISABLE |
+					SVSMUNIT_CLOCK_GATE_DISABLE);
+		}
+
+		OUTREG(PCH_DSPCLK_GATE_D, dspclk_gate);
+	} else if (IS_G4X(intel)) {
 		uint32_t dspclk_gate;
 		OUTREG(RENCLK_GATE_D1, 0);
 		OUTREG(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@@ -1629,27 +1649,27 @@ static Bool SaveHWState(ScrnInfoPtr scrn)
 	i830_save_palette(intel, PIPE_A);
 
 	if(xf86_config->num_crtc == 2) {
-	intel->savePIPEBCONF = INREG(PIPEBCONF);
-	intel->savePIPEBSRC = INREG(PIPEBSRC);
-	intel->saveDSPBCNTR = INREG(DSPBCNTR);
-	intel->saveFPB0 = INREG(FPB0);
-	intel->saveFPB1 = INREG(FPB1);
-	intel->saveDPLL_B = INREG(DPLL_B);
-	if (IS_I965G(intel))
-		intel->saveDPLL_B_MD = INREG(DPLL_B_MD);
-	intel->saveHTOTAL_B = INREG(HTOTAL_B);
-	intel->saveHBLANK_B = INREG(HBLANK_B);
-	intel->saveHSYNC_B = INREG(HSYNC_B);
-	intel->saveVTOTAL_B = INREG(VTOTAL_B);
-	intel->saveVBLANK_B = INREG(VBLANK_B);
-	intel->saveVSYNC_B = INREG(VSYNC_B);
-	intel->saveBCLRPAT_B = INREG(BCLRPAT_B);
-	intel->saveDSPBSTRIDE = INREG(DSPBSTRIDE);
-	intel->saveDSPBSIZE = INREG(DSPBSIZE);
-	intel->saveDSPBPOS = INREG(DSPBPOS);
-	intel->saveDSPBBASE = INREG(DSPBBASE);
-
-	i830_save_palette(intel, PIPE_B);
+		intel->savePIPEBCONF = INREG(PIPEBCONF);
+		intel->savePIPEBSRC = INREG(PIPEBSRC);
+		intel->saveDSPBCNTR = INREG(DSPBCNTR);
+		intel->saveFPB0 = INREG(FPB0);
+		intel->saveFPB1 = INREG(FPB1);
+		intel->saveDPLL_B = INREG(DPLL_B);
+		if (IS_I965G(intel))
+			intel->saveDPLL_B_MD = INREG(DPLL_B_MD);
+		intel->saveHTOTAL_B = INREG(HTOTAL_B);
+		intel->saveHBLANK_B = INREG(HBLANK_B);
+		intel->saveHSYNC_B = INREG(HSYNC_B);
+		intel->saveVTOTAL_B = INREG(VTOTAL_B);
+		intel->saveVBLANK_B = INREG(VBLANK_B);
+		intel->saveVSYNC_B = INREG(VSYNC_B);
+		intel->saveBCLRPAT_B = INREG(BCLRPAT_B);
+		intel->saveDSPBSTRIDE = INREG(DSPBSTRIDE);
+		intel->saveDSPBSIZE = INREG(DSPBSIZE);
+		intel->saveDSPBPOS = INREG(DSPBPOS);
+		intel->saveDSPBBASE = INREG(DSPBBASE);
+
+		i830_save_palette(intel, PIPE_B);
 	}
 
 	if (IS_I965G(intel)) {
diff --git a/src/intel_driver.h b/src/intel_driver.h
index c1fb92b9..7042bd49 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -262,9 +262,14 @@
 			IS_I965G(pI810) ||			\
 			IS_G33CLASS(pI810))
 
+#define IS_GEN6_M(pI810) ((pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT1  || \
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
+
+
 #define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
 
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810)) || IS_GEN6_m(pI810)
 /* mark chipsets for using gfx VM offset for overlay */
 #define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
 /* mark chipsets without overlay hw */