diff options
| author | Keith Packard <keithp@neko.keithp.com> | 2007-06-22 16:32:46 +0100 |
|---|---|---|
| committer | Keith Packard <keithp@neko.keithp.com> | 2007-06-22 16:32:46 +0100 |
| commit | ec236c76b93aea5f2ee1e8b8509cde4625974fcb (patch) | |
| tree | ae6b4cf1fa5be91719b45f3791735cc4e98ffd6d | |
| parent | d957c6b8e1dde8e11c1db3431e0ff58c5d984880 (diff) | |
I830 needs to have plane/pipe/pll started in mode_set.
The patch for the i855 to stop enabling plane/pipe/pll in mode_set broke the
i830. Revert that just for the i830, leaving it enabled for the i855.
| -rw-r--r-- | src/i830_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/i830_display.c b/src/i830_display.c index 1f0f5b80..f6e99be0 100644 --- a/src/i830_display.c +++ b/src/i830_display.c @@ -963,7 +963,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, * will be run after the mode is set. On 9xx, it helps. * On 855, it can lock up the chip (and the entire machine) */ - if (IS_I9XX (pI830)) + if (!IS_I85X (pI830)) { dspcntr |= DISPLAY_PLANE_ENABLE; pipeconf |= PIPEACONF_ENABLE; |