Merge branch 'master' into pfit

author: Jesse Barnes <jbarnes@nietzche.virtuousgeek.org> 2008-03-17 15:19:05 -0700
committer: Jesse Barnes <jbarnes@nietzche.virtuousgeek.org> 2008-03-17 15:19:05 -0700
commit: ffb5a115cc62ed63110f77815b7f04976f720065 (patch)
tree: bebc956a00ed8a302e3df575eb0ee0249cc12ca9
parent: 05cf07071e25f84dec3476a9bed7235ed50cd249 (diff)
parent: 24e6eb2ae683ed6614ac79c0d7811ac9fe94209f (diff)
20 files changed, 963 insertions, 986 deletions
diff --git a/src/i830.h b/src/i830.h
index 6c3fa522..ee0f03ad 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -686,6 +686,8 @@ extern void i830_crtc_dpms_video(xf86CrtcPtr crtc, Bool on);
 int
 i830_crtc_pipe (xf86CrtcPtr crtc);
 
+extern xf86CrtcPtr i830_pipe_to_crtc(ScrnInfoPtr pScrn, int pipe);
+
 Bool
 i830_pipe_a_require_activate (ScrnInfoPtr scrn);
 
@@ -828,6 +830,13 @@ static inline int i830_fb_compression_supported(I830Ptr pI830)
 
 Bool i830_pixmap_tiled(PixmapPtr p);
 
+/* Batchbuffer compatibility handling */
+#define BEGIN_BATCH(n) BEGIN_LP_RING(n)
+#define ENSURE_BATCH(n)
+#define OUT_BATCH(d) OUT_RING(d)
+#define OUT_BATCH_F(x) OUT_RING_F(x)
+#define ADVANCE_BATCH() ADVANCE_LP_RING()
+
 extern const int I830PatternROP[16];
 extern const int I830CopyROP[16];
 
diff --git a/src/i830_3d.c b/src/i830_3d.c
index 45e02c4d..ee17f25d 100644
--- a/src/i830_3d.c
+++ b/src/i830_3d.c
@@ -38,65 +38,65 @@ void I830EmitInvarientState( ScrnInfoPtr pScrn )
 {
    I830Ptr pI830 = I830PTR(pScrn);
 
-   BEGIN_LP_RING(58);
+   BEGIN_BATCH(58);
 
-   OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
-   OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
-   OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
-   OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
+   OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
+   OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
+   OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
+   OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
 
-   OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_DFLT_Z_CMD);
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_FOG_MODE_CMD);
-   OUT_RING(FOGFUNC_ENABLE |
+   OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
+   OUT_BATCH(FOGFUNC_ENABLE |
 	     FOG_LINEAR_CONST | 
 	     FOGSRC_INDEX_Z | 
 	     ENABLE_FOG_DENSITY);
-   OUT_RING(0);
-   OUT_RING(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
+   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 	     MAP_UNIT(0) |
 	     DISABLE_TEX_STREAM_BUMP |
 	     ENABLE_TEX_STREAM_COORD_SET |
 	     TEX_STREAM_COORD_SET(0) |
 	     ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
-   OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
+   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 	     MAP_UNIT(1) |
 	     DISABLE_TEX_STREAM_BUMP |
 	     ENABLE_TEX_STREAM_COORD_SET |
 	     TEX_STREAM_COORD_SET(1) |
 	     ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
-   OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
+   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 	     MAP_UNIT(2) |
 	     DISABLE_TEX_STREAM_BUMP |
 	     ENABLE_TEX_STREAM_COORD_SET |
 	     TEX_STREAM_COORD_SET(2) |
 	     ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
-   OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
+   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 	     MAP_UNIT(3) |
 	     DISABLE_TEX_STREAM_BUMP |
 	     ENABLE_TEX_STREAM_COORD_SET |
 	     TEX_STREAM_COORD_SET(3) |
 	     ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
 
-   OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
-   OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
-   OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
-   OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
-   OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
-   OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
-   OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
-   OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
+   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
+   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
+   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
+   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
+   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
+   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
+   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
+   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
 
-   OUT_RING(_3DSTATE_RASTER_RULES_CMD |
+   OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 	     ENABLE_POINT_RASTER_RULE |
 	     OGL_POINT_RASTER_RULE |
 	     ENABLE_LINE_STRIP_PROVOKE_VRTX |
@@ -106,147 +106,147 @@ void I830EmitInvarientState( ScrnInfoPtr pScrn )
 	     TRI_FAN_PROVOKE_VRTX(2) | 
 	     TRI_STRIP_PROVOKE_VRTX(2));
 
-   OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD | 
+   OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD |
 	     DISABLE_SCISSOR_RECT);
 
-   OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD);
-   OUT_RING(0);
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_VERTEX_TRANSFORM);
-   OUT_RING(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
+   OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
+   OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
 
-   OUT_RING(_3DSTATE_W_STATE_CMD);
-   OUT_RING(MAGIC_W_STATE_DWORD1);
-   OUT_RING(0x3f800000 /* 1.0 in IEEE float */ );
+   OUT_BATCH(_3DSTATE_W_STATE_CMD);
+   OUT_BATCH(MAGIC_W_STATE_DWORD1);
+   OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
 
-   OUT_RING(_3DSTATE_COLOR_FACTOR_CMD);
-   OUT_RING(0x80808080);	/* .5 required in alpha for GL_DOT3_RGBA_EXT */
+   OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
+   OUT_BATCH(0x80808080);	/* .5 required in alpha for GL_DOT3_RGBA_EXT */
 
-   OUT_RING(_3DSTATE_MAP_COORD_SETBIND_CMD);
-   OUT_RING(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
-   	TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
-   	TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
-   	TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
+   OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
+   OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
+	     TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
+	     TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
+	     TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
 
    /* copy from mesa */
-   OUT_RING(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
-	   DISABLE_INDPT_ALPHA_BLEND |
-	   ENABLE_ALPHA_BLENDFUNC |
-	   ABLENDFUNC_ADD);
-
-   OUT_RING(_3DSTATE_FOG_COLOR_CMD |
-	   FOG_COLOR_RED(0) |
-	   FOG_COLOR_GREEN(0) |
-	   FOG_COLOR_BLUE(0));
-
-   OUT_RING(_3DSTATE_CONST_BLEND_COLOR_CMD);
-   OUT_RING(0);
-
-   OUT_RING(_3DSTATE_MODES_1_CMD |
-	   ENABLE_COLR_BLND_FUNC |
-	   BLENDFUNC_ADD |
-	   ENABLE_SRC_BLND_FACTOR |
-	   SRC_BLND_FACT(BLENDFACTOR_ONE) |
-	   ENABLE_DST_BLND_FACTOR |
-	   DST_BLND_FACT(BLENDFACTOR_ZERO)); 
-   OUT_RING(_3DSTATE_MODES_2_CMD |
-	   ENABLE_GLOBAL_DEPTH_BIAS |
-	   GLOBAL_DEPTH_BIAS(0) |
-	   ENABLE_ALPHA_TEST_FUNC|
-	   ALPHA_TEST_FUNC(0) | /* always */
-	   ALPHA_REF_VALUE(0));
-   OUT_RING(_3DSTATE_MODES_3_CMD |
-	   ENABLE_DEPTH_TEST_FUNC |
-	   DEPTH_TEST_FUNC(0x2) | /* COMPAREFUNC_LESS */
-	   ENABLE_ALPHA_SHADE_MODE |
-	   ALPHA_SHADE_MODE(SHADE_MODE_LINEAR)
-	   | ENABLE_FOG_SHADE_MODE |
-	   FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
-	   ENABLE_SPEC_SHADE_MODE |
-	   SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
-	   ENABLE_COLOR_SHADE_MODE |
-	   COLOR_SHADE_MODE(SHADE_MODE_LINEAR)
-	   | ENABLE_CULL_MODE | CULLMODE_NONE);
-
-   OUT_RING(_3DSTATE_MODES_4_CMD |
-	   ENABLE_LOGIC_OP_FUNC |
-	   LOGIC_OP_FUNC(LOGICOP_COPY) |
-	   ENABLE_STENCIL_TEST_MASK |
-	   STENCIL_TEST_MASK(0xff) |
-	   ENABLE_STENCIL_WRITE_MASK |
-	   STENCIL_WRITE_MASK(0xff));
-
-   OUT_RING(_3DSTATE_STENCIL_TEST_CMD |
-	   ENABLE_STENCIL_PARMS |
-	   STENCIL_FAIL_OP(0) | /* STENCILOP_KEEP */
-	   STENCIL_PASS_DEPTH_FAIL_OP(0) | /* STENCILOP_KEEP */
-	   STENCIL_PASS_DEPTH_PASS_OP(0) | /* STENCILOP_KEEP */
-	   ENABLE_STENCIL_TEST_FUNC |
-	   STENCIL_TEST_FUNC(0) | /* COMPAREFUNC_ALWAYS */
-	   ENABLE_STENCIL_REF_VALUE |
-	   STENCIL_REF_VALUE(0));
-
-   OUT_RING(_3DSTATE_MODES_5_CMD |
-	   FLUSH_TEXTURE_CACHE |
-	   ENABLE_SPRITE_POINT_TEX |
-	   SPRITE_POINT_TEX_OFF |
-	   ENABLE_FIXED_LINE_WIDTH |
-	   FIXED_LINE_WIDTH(0x2) |       /* 1.0 */
-	   ENABLE_FIXED_POINT_WIDTH |
-	   FIXED_POINT_WIDTH(1));
-
-   OUT_RING(_3DSTATE_ENABLES_1_CMD |
-	   DISABLE_LOGIC_OP |
-	   DISABLE_STENCIL_TEST |
-	   DISABLE_DEPTH_BIAS |
-	   DISABLE_SPEC_ADD |
-	   DISABLE_FOG |
-	   DISABLE_ALPHA_TEST |
-	   ENABLE_COLOR_BLEND |
-	   DISABLE_DEPTH_TEST);
-   OUT_RING(_3DSTATE_ENABLES_2_CMD |
-	   DISABLE_STENCIL_WRITE |
-	   ENABLE_TEX_CACHE |
-	   DISABLE_DITHER |			
-	   ENABLE_COLOR_MASK |
-	   ENABLE_COLOR_WRITE |
-	   DISABLE_DEPTH_WRITE);
-
-   OUT_RING(_3DSTATE_STIPPLE); 
+   OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
+	     DISABLE_INDPT_ALPHA_BLEND |
+	     ENABLE_ALPHA_BLENDFUNC |
+	     ABLENDFUNC_ADD);
+
+   OUT_BATCH(_3DSTATE_FOG_COLOR_CMD |
+	     FOG_COLOR_RED(0) |
+	     FOG_COLOR_GREEN(0) |
+	     FOG_COLOR_BLUE(0));
+
+   OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
+   OUT_BATCH(0);
+
+   OUT_BATCH(_3DSTATE_MODES_1_CMD |
+	     ENABLE_COLR_BLND_FUNC |
+	     BLENDFUNC_ADD |
+	     ENABLE_SRC_BLND_FACTOR |
+	     SRC_BLND_FACT(BLENDFACTOR_ONE) |
+	     ENABLE_DST_BLND_FACTOR |
+	     DST_BLND_FACT(BLENDFACTOR_ZERO));
+   OUT_BATCH(_3DSTATE_MODES_2_CMD |
+	     ENABLE_GLOBAL_DEPTH_BIAS |
+	     GLOBAL_DEPTH_BIAS(0) |
+	     ENABLE_ALPHA_TEST_FUNC|
+	     ALPHA_TEST_FUNC(0) | /* always */
+	     ALPHA_REF_VALUE(0));
+   OUT_BATCH(_3DSTATE_MODES_3_CMD |
+	     ENABLE_DEPTH_TEST_FUNC |
+	     DEPTH_TEST_FUNC(0x2) | /* COMPAREFUNC_LESS */
+	     ENABLE_ALPHA_SHADE_MODE |
+	     ALPHA_SHADE_MODE(SHADE_MODE_LINEAR) |
+	     ENABLE_FOG_SHADE_MODE |
+	     FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
+	     ENABLE_SPEC_SHADE_MODE |
+	     SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
+	     ENABLE_COLOR_SHADE_MODE |
+	     COLOR_SHADE_MODE(SHADE_MODE_LINEAR) |
+	     ENABLE_CULL_MODE | CULLMODE_NONE);
+
+   OUT_BATCH(_3DSTATE_MODES_4_CMD |
+	     ENABLE_LOGIC_OP_FUNC |
+	     LOGIC_OP_FUNC(LOGICOP_COPY) |
+	     ENABLE_STENCIL_TEST_MASK |
+	     STENCIL_TEST_MASK(0xff) |
+	     ENABLE_STENCIL_WRITE_MASK |
+	     STENCIL_WRITE_MASK(0xff));
+
+   OUT_BATCH(_3DSTATE_STENCIL_TEST_CMD |
+	     ENABLE_STENCIL_PARMS |
+	     STENCIL_FAIL_OP(0) | /* STENCILOP_KEEP */
+	     STENCIL_PASS_DEPTH_FAIL_OP(0) | /* STENCILOP_KEEP */
+	     STENCIL_PASS_DEPTH_PASS_OP(0) | /* STENCILOP_KEEP */
+	     ENABLE_STENCIL_TEST_FUNC |
+	     STENCIL_TEST_FUNC(0) | /* COMPAREFUNC_ALWAYS */
+	     ENABLE_STENCIL_REF_VALUE |
+	     STENCIL_REF_VALUE(0));
+
+   OUT_BATCH(_3DSTATE_MODES_5_CMD |
+	     FLUSH_TEXTURE_CACHE |
+	     ENABLE_SPRITE_POINT_TEX |
+	     SPRITE_POINT_TEX_OFF |
+	     ENABLE_FIXED_LINE_WIDTH |
+	     FIXED_LINE_WIDTH(0x2) |       /* 1.0 */
+	     ENABLE_FIXED_POINT_WIDTH |
+	     FIXED_POINT_WIDTH(1));
+
+   OUT_BATCH(_3DSTATE_ENABLES_1_CMD |
+	     DISABLE_LOGIC_OP |
+	     DISABLE_STENCIL_TEST |
+	     DISABLE_DEPTH_BIAS |
+	     DISABLE_SPEC_ADD |
+	     DISABLE_FOG |
+	     DISABLE_ALPHA_TEST |
+	     ENABLE_COLOR_BLEND |
+	     DISABLE_DEPTH_TEST);
+   OUT_BATCH(_3DSTATE_ENABLES_2_CMD |
+	     DISABLE_STENCIL_WRITE |
+	     ENABLE_TEX_CACHE |
+	     DISABLE_DITHER |
+	     ENABLE_COLOR_MASK |
+	     ENABLE_COLOR_WRITE |
+	     DISABLE_DEPTH_WRITE);
+
+   OUT_BATCH(_3DSTATE_STIPPLE);
 
    /* Set default blend state */
-   OUT_RING(_3DSTATE_MAP_BLEND_OP_CMD(0) |
-	   TEXPIPE_COLOR |
-	   ENABLE_TEXOUTPUT_WRT_SEL |
-	   TEXOP_OUTPUT_CURRENT |
-	   DISABLE_TEX_CNTRL_STAGE |
-	   TEXOP_SCALE_1X |
-	   TEXOP_MODIFY_PARMS |
-	   TEXOP_LAST_STAGE | TEXBLENDOP_ARG1);
-   OUT_RING(_3DSTATE_MAP_BLEND_OP_CMD(0) |
-	   TEXPIPE_ALPHA |
-	   ENABLE_TEXOUTPUT_WRT_SEL |
-	   TEXOP_OUTPUT_CURRENT |
-	   TEXOP_SCALE_1X |
-	   TEXOP_MODIFY_PARMS | TEXBLENDOP_ARG1);
-   OUT_RING(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
-	   TEXPIPE_COLOR |
-	   TEXBLEND_ARG1 |
-	   TEXBLENDARG_MODIFY_PARMS |
-	   TEXBLENDARG_DIFFUSE);
-   OUT_RING(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
-	   TEXPIPE_ALPHA |
-	   TEXBLEND_ARG1 |
-	   TEXBLENDARG_MODIFY_PARMS |
-	   TEXBLENDARG_DIFFUSE);
-
-   OUT_RING(_3DSTATE_AA_CMD |
-	   AA_LINE_ECAAR_WIDTH_ENABLE |
-	   AA_LINE_ECAAR_WIDTH_1_0 |
-	   AA_LINE_REGION_WIDTH_ENABLE |
-	   AA_LINE_REGION_WIDTH_1_0 |
-	   AA_LINE_DISABLE);
-
-   ADVANCE_LP_RING();
+   OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) |
+	     TEXPIPE_COLOR |
+	     ENABLE_TEXOUTPUT_WRT_SEL |
+	     TEXOP_OUTPUT_CURRENT |
+	     DISABLE_TEX_CNTRL_STAGE |
+	     TEXOP_SCALE_1X |
+	     TEXOP_MODIFY_PARMS |
+	     TEXOP_LAST_STAGE | TEXBLENDOP_ARG1);
+   OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) |
+	     TEXPIPE_ALPHA |
+	     ENABLE_TEXOUTPUT_WRT_SEL |
+	     TEXOP_OUTPUT_CURRENT |
+	     TEXOP_SCALE_1X |
+	     TEXOP_MODIFY_PARMS | TEXBLENDOP_ARG1);
+   OUT_BATCH(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
+	     TEXPIPE_COLOR |
+	     TEXBLEND_ARG1 |
+	     TEXBLENDARG_MODIFY_PARMS |
+	     TEXBLENDARG_DIFFUSE);
+   OUT_BATCH(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
+	     TEXPIPE_ALPHA |
+	     TEXBLEND_ARG1 |
+	     TEXBLENDARG_MODIFY_PARMS |
+	     TEXBLENDARG_DIFFUSE);
+
+   OUT_BATCH(_3DSTATE_AA_CMD |
+	     AA_LINE_ECAAR_WIDTH_ENABLE |
+	     AA_LINE_ECAAR_WIDTH_1_0 |
+	     AA_LINE_REGION_WIDTH_ENABLE |
+	     AA_LINE_REGION_WIDTH_1_0 |
+	     AA_LINE_DISABLE);
+
+   ADVANCE_BATCH();
 }
diff --git a/src/i830_accel.c b/src/i830_accel.c
index fdc713be..953a73bc 100644
--- a/src/i830_accel.c
+++ b/src/i830_accel.c
@@ -195,10 +195,10 @@ I830Sync(ScrnInfoPtr pScrn)
     */
    
    {
-      BEGIN_LP_RING(2);
-      OUT_RING(MI_FLUSH | flags);
-      OUT_RING(MI_NOOP);		/* pad to quadword */
-      ADVANCE_LP_RING();
+      BEGIN_BATCH(2);
+      OUT_BATCH(MI_FLUSH | flags);
+      OUT_BATCH(MI_NOOP);		/* pad to quadword */
+      ADVANCE_BATCH();
    }
 
    I830WaitLpRing(pScrn, pI830->LpRing->mem->size - 8, 0);
@@ -217,10 +217,10 @@ I830EmitFlush(ScrnInfoPtr pScrn)
       flags = 0;
 
    {
-       BEGIN_LP_RING(2);
-       OUT_RING(MI_FLUSH | flags);
-       OUT_RING(MI_NOOP);		/* pad to quadword */
-       ADVANCE_LP_RING();
+       BEGIN_BATCH(2);
+       OUT_BATCH(MI_FLUSH | flags);
+       OUT_BATCH(MI_NOOP);		/* pad to quadword */
+       ADVANCE_BATCH();
    }
 }
 
diff --git a/src/i830_crt.c b/src/i830_crt.c
index 3705233b..d1ed3a81 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -391,6 +391,16 @@ i830_crt_destroy (xf86OutputPtr output)
 	xfree (output->driver_private);
 }
 
+static xf86CrtcPtr
+i830_crt_get_crtc(xf86OutputPtr output)
+{
+    ScrnInfoPtr	pScrn = output->scrn;
+    I830Ptr pI830 = I830PTR(pScrn);
+    int pipe = !!(INREG(ADPA) & ADPA_PIPE_SELECT_MASK);
+   
+    return i830_pipe_to_crtc(pScrn, pipe);
+}
+
 static const xf86OutputFuncsRec i830_crt_output_funcs = {
     .dpms = i830_crt_dpms,
     .save = i830_crt_save,
@@ -402,7 +412,10 @@ static const xf86OutputFuncsRec i830_crt_output_funcs = {
     .commit = i830_output_commit,
     .detect = i830_crt_detect,
     .get_modes = i830_ddc_get_modes,
-    .destroy = i830_crt_destroy
+    .destroy = i830_crt_destroy,
+#ifdef RANDR_GET_CRTC_INTERFACE
+    .get_crtc = i830_crt_get_crtc,
+#endif
 };
 
 void
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 768c724f..5d2539e6 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -1008,16 +1008,16 @@ I830DRIDoRefreshArea (ScrnInfoPtr pScrn, int num, BoxPtr pbox, uint32_t dst)
    }
 
    for (i = 0 ; i < num ; i++, pbox++) {
-      BEGIN_LP_RING(8);
-      OUT_RING(cmd);
-      OUT_RING(br13);
-      OUT_RING((pbox->y1 << 16) | pbox->x1);
-      OUT_RING((pbox->y2 << 16) | pbox->x2);
-      OUT_RING(dst);
-      OUT_RING((pbox->y1 << 16) | pbox->x1);
-      OUT_RING(br13 & 0xffff);
-      OUT_RING(pI830->front_buffer->offset);
-      ADVANCE_LP_RING();
+      BEGIN_BATCH(8);
+      OUT_BATCH(cmd);
+      OUT_BATCH(br13);
+      OUT_BATCH((pbox->y1 << 16) | pbox->x1);
+      OUT_BATCH((pbox->y2 << 16) | pbox->x2);
+      OUT_BATCH(dst);
+      OUT_BATCH((pbox->y1 << 16) | pbox->x1);
+      OUT_BATCH(br13 & 0xffff);
+      OUT_BATCH(pI830->front_buffer->offset);
+      ADVANCE_BATCH();
    }
 }
 
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 644a11c9..e1ab5364 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2341,12 +2341,12 @@ IntelEmitInvarientState(ScrnInfoPtr pScrn)
    ctx_addr = pI830->logical_context->offset;
    assert((pI830->logical_context->offset & 2047) == 0);
    {
-      BEGIN_LP_RING(2);
-      OUT_RING(MI_SET_CONTEXT);
-      OUT_RING(pI830->logical_context->offset |
-	       CTXT_NO_RESTORE |
-	       CTXT_PALETTE_SAVE_DISABLE | CTXT_PALETTE_RESTORE_DISABLE);
-      ADVANCE_LP_RING();
+      BEGIN_BATCH(2);
+      OUT_BATCH(MI_SET_CONTEXT);
+      OUT_BATCH(pI830->logical_context->offset |
+		CTXT_NO_RESTORE |
+		CTXT_PALETTE_SAVE_DISABLE | CTXT_PALETTE_RESTORE_DISABLE);
+      ADVANCE_BATCH();
    }
 
    if (!IS_I965G(pI830))
@@ -3165,8 +3165,6 @@ I830EnterVT(int scrnIndex, int flags)
 {
    ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
    I830Ptr  pI830 = I830PTR(pScrn);
-   xf86CrtcConfigPtr	config = XF86_CRTC_CONFIG_PTR(pScrn);
-   int o;
 
    DPRINTF(PFX, "Enter VT\n");
 
@@ -3213,11 +3211,6 @@ I830EnterVT(int scrnIndex, int flags)
    memset(pI830->FbBase + pScrn->fbOffset, 0,
 	  pScrn->virtualY * pScrn->displayWidth * pI830->cpp);
 
-   for (o = 0; o < config->num_output; o++) {
-   	xf86OutputPtr  output = config->output[o];
-	output->funcs->dpms(output, DPMSModeOff);
-   }
-
    if (!xf86SetDesiredModes (pScrn))
       return FALSE;
    
@@ -3483,6 +3476,23 @@ I830PMEvent(int scrnIndex, pmEvent event, Bool undo)
    return TRUE;
 }
 
+xf86CrtcPtr
+i830_pipe_to_crtc(ScrnInfoPtr pScrn, int pipe)
+{
+   xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (pScrn);
+   int c;
+   
+   for (c = 0; c < config->num_crtc; c++) {
+      xf86CrtcPtr crtc = config->crtc[c];
+      I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+
+      if (intel_crtc->pipe == pipe)
+	  return crtc;
+   }
+
+   return NULL;
+} 
+
 #if 0
 /**
  * This function is used for testing of the screen detect functions from the
diff --git a/src/i830_dvo.c b/src/i830_dvo.c
index c0f76e30..75618333 100644
--- a/src/i830_dvo.c
+++ b/src/i830_dvo.c
@@ -330,6 +330,18 @@ i830_dvo_destroy (xf86OutputPtr output)
     }
 }
 
+static xf86CrtcPtr
+i830_dvo_get_crtc(xf86OutputPtr output)
+{
+    ScrnInfoPtr	pScrn = output->scrn;
+    I830Ptr pI830 = I830PTR(pScrn);
+    I830OutputPrivatePtr intel_output = output->driver_private;
+    struct _I830DVODriver *drv = intel_output->i2c_drv;
+    int pipe = !!(INREG(drv->dvo_reg) & SDVO_PIPE_B_SELECT);
+   
+    return i830_pipe_to_crtc(pScrn, pipe);
+}
+
 static const xf86OutputFuncsRec i830_dvo_output_funcs = {
     .dpms = i830_dvo_dpms,
     .save = i830_dvo_save,
@@ -341,7 +353,10 @@ static const xf86OutputFuncsRec i830_dvo_output_funcs = {
     .commit = i830_output_commit,
     .detect = i830_dvo_detect,
     .get_modes = i830_dvo_get_modes,
-    .destroy = i830_dvo_destroy
+    .destroy = i830_dvo_destroy,
+#ifdef RANDR_GET_CRTC_INTERFACE
+    .get_crtc = i830_dvo_get_crtc,
+#endif
 };
 
 /**
diff --git a/src/i830_exa.c b/src/i830_exa.c
index 1f6bf1d9..bf9fc669 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -207,7 +207,7 @@ I830EXASolid(PixmapPtr pPixmap, int x1, int y1, int x2, int y2)
     pitch = exaGetPixmapPitch(pPixmap);
 
     {
-	BEGIN_LP_RING(6);
+	BEGIN_BATCH(6);
 
 	cmd = XY_COLOR_BLT_CMD;
 
@@ -220,14 +220,14 @@ I830EXASolid(PixmapPtr pPixmap, int x1, int y1, int x2, int y2)
 	    cmd |= XY_COLOR_BLT_TILED;
 	}
 
-	OUT_RING(cmd);
+	OUT_BATCH(cmd);
 
-	OUT_RING(pI830->BR[13] | pitch);
-	OUT_RING((y1 << 16) | (x1 & 0xffff));
-	OUT_RING((y2 << 16) | (x2 & 0xffff));
-	OUT_RING(offset);
-	OUT_RING(pI830->BR[16]);
-	ADVANCE_LP_RING();
+	OUT_BATCH(pI830->BR[13] | pitch);
+	OUT_BATCH((y1 << 16) | (x1 & 0xffff));
+	OUT_BATCH((y2 << 16) | (x2 & 0xffff));
+	OUT_BATCH(offset);
+	OUT_BATCH(pI830->BR[16]);
+	ADVANCE_BATCH();
     }
 }
 
@@ -291,7 +291,7 @@ I830EXACopy(PixmapPtr pDstPixmap, int src_x1, int src_y1, int dst_x1,
     src_pitch = exaGetPixmapPitch(pI830->pSrcPixmap);
 
     {
-	BEGIN_LP_RING(8);
+	BEGIN_BATCH(8);
 
 	cmd = XY_SRC_COPY_BLT_CMD;
 
@@ -312,17 +312,17 @@ I830EXACopy(PixmapPtr pDstPixmap, int src_x1, int src_y1, int dst_x1,
 	    }
 	}
 
-	OUT_RING(cmd);
+	OUT_BATCH(cmd);
 
-	OUT_RING(pI830->BR[13] | dst_pitch);
-	OUT_RING((dst_y1 << 16) | (dst_x1 & 0xffff));
-	OUT_RING((dst_y2 << 16) | (dst_x2 & 0xffff));
-	OUT_RING(dst_off);
-	OUT_RING((src_y1 << 16) | (src_x1 & 0xffff));
-	OUT_RING(src_pitch);
-	OUT_RING(src_off);
+	OUT_BATCH(pI830->BR[13] | dst_pitch);
+	OUT_BATCH((dst_y1 << 16) | (dst_x1 & 0xffff));
+	OUT_BATCH((dst_y2 << 16) | (dst_x2 & 0xffff));
+	OUT_BATCH(dst_off);
+	OUT_BATCH((src_y1 << 16) | (src_x1 & 0xffff));
+	OUT_BATCH(src_pitch);
+	OUT_BATCH(src_off);
 
-	ADVANCE_LP_RING();
+	ADVANCE_BATCH();
     }
 }
 
@@ -363,93 +363,6 @@ i830_get_transformed_coordinates(int x, int y, PictTransformPtr transform,
     }
 }
 
-/**
- * Uploads data from system memory to the framebuffer using a series of
- * 8x8 pattern blits.
- */
-static Bool
-i830_upload_to_screen(PixmapPtr pDst, int x, int y, int w, int h, char *src,
-		      int src_pitch)
-{
-    ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
-    I830Ptr pI830 = I830PTR(pScrn);
-    const int uts_width_max = 16, uts_height_max = 16;
-    int cpp = pDst->drawable.bitsPerPixel / 8;
-    int sub_x, sub_y;
-    uint32_t br13;
-    uint32_t offset;
-
-    if (w > uts_width_max || h > uts_height_max)
-	I830FALLBACK("too large for upload to screen (%d,%d)", w, h);
-
-    offset = exaGetPixmapOffset(pDst);
-
-    br13 = exaGetPixmapPitch(pDst);
-    br13 |= ((I830PatternROP[GXcopy] & 0xff) << 16);
-    switch (pDst->drawable.bitsPerPixel) {
-    case 16:
-	br13 |= 1 << 24;
-	break;
-    case 32:
-	br13 |= 3 << 24;
-	break;
-    }
-
-    for (sub_y = 0; sub_y < uts_height_max && sub_y < h; sub_y += 8) {
-	int sub_height;
-
-	if (sub_y + 8 > h)
-	    sub_height = h - sub_y;
-	else
-	    sub_height = 8;
-
-	for (sub_x = 0; sub_x < uts_width_max && sub_x < w; sub_x += 8) {
-	    int sub_width, line;
-	    char *src_line = src + sub_y * src_pitch + sub_x * cpp;
-
-	    if (sub_x + 8 > w)
-		sub_width = w - sub_x;
-	    else
-		sub_width = 8;
-
-	    BEGIN_LP_RING(6 + (cpp * 8 * 8 / 4));
-
-	    /* XXX We may need a pattern offset here for {x,y} % 8 != 0*/
-	    OUT_RING(XY_PAT_BLT_IMMEDIATE |
-		     XY_SRC_COPY_BLT_WRITE_ALPHA |
-		     XY_SRC_COPY_BLT_WRITE_RGB |
-		     (3 + cpp * 8 * 8 / 4));
-	    OUT_RING(br13);
-	    OUT_RING(((y + sub_y) << 16) | (x + sub_x));
-	    OUT_RING(((y + sub_y + sub_height) << 16) |
-		     (x + sub_x + sub_width));
-	    OUT_RING(offset);
-
-	    /* Write out the lines with valid data, followed by any needed
-	     * padding
-	     */
-	    for (line = 0; line < sub_height; line++) {
-		OUT_RING_COPY(sub_width * cpp, src_line);
-		src_line += src_pitch;
-		if (sub_width != 8)
-		    OUT_RING_PAD((8 - sub_width) * cpp);
-	    }
-	    /* Write out any full padding lines to follow */
-	    if (sub_height != 8)
-		OUT_RING_PAD(8 * cpp * (8 - sub_height));
-
-	    OUT_RING(MI_NOOP);
-	    ADVANCE_LP_RING();
-	}
-    }
-
-    exaMarkSync(pDst->drawable.pScreen);
-    /* exaWaitSync(pDst->drawable.pScreen); */
-
-    return TRUE;
-}
-
-
 /*
  * TODO:
  *   - Dual head?
@@ -584,10 +497,6 @@ I830EXAInit(ScreenPtr pScreen)
     pI830->EXADriverPtr->PixmapIsOffscreen = i830_exa_pixmap_is_offscreen;
 #endif
 
-    /* UploadToScreen/DownloadFromScreen */
-    if (0)
-	pI830->EXADriverPtr->UploadToScreen = i830_upload_to_screen;
-
     if(!exaDriverInit(pScreen, pI830->EXADriverPtr)) {
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 		   "EXA initialization failed; trying older version\n");
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index daf71da7..01f5a414 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -1165,6 +1165,16 @@ i830_lvds_get_property(xf86OutputPtr output, Atom property)
 }
 #endif /* RANDR_13_INTERFACE */
 
+static xf86CrtcPtr
+i830_lvds_get_crtc(xf86OutputPtr output)
+{
+    ScrnInfoPtr	pScrn = output->scrn;
+    I830Ptr pI830 = I830PTR(pScrn);
+    int pipe = !!(INREG(LVDS) & LVDS_PIPEB_SELECT);
+   
+    return i830_pipe_to_crtc(pScrn, pipe);
+}
+
 static const xf86OutputFuncsRec i830_lvds_output_funcs = {
     .create_resources = i830_lvds_create_resources,
     .dpms = i830_lvds_dpms,
@@ -1183,7 +1193,10 @@ static const xf86OutputFuncsRec i830_lvds_output_funcs = {
 #ifdef RANDR_13_INTERFACE
     .get_property = i830_lvds_get_property,
 #endif
-    .destroy = i830_lvds_destroy
+    .destroy = i830_lvds_destroy,
+#ifdef RANDR_GET_CRTC_INTERFACE
+    .get_crtc = i830_lvds_get_crtc,
+#endif
 };
 
 void
diff --git a/src/i830_render.c b/src/i830_render.c
index 1bb01034..949c7006 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -312,38 +312,38 @@ i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
 	else
 	    format |= MAPSURF_32BIT;
 
-	BEGIN_LP_RING(10);
-	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
-	OUT_RING((offset & TM0S0_ADDRESS_MASK) | TM0S0_USE_FENCE); 
-	OUT_RING(((pPix->drawable.height - 1) << TM0S1_HEIGHT_SHIFT) |
-		((pPix->drawable.width - 1) << TM0S1_WIDTH_SHIFT) | format);
-	OUT_RING((pitch/4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
-	OUT_RING(filter);
-	OUT_RING(0); /* default color */
-	OUT_RING(_3DSTATE_MAP_COORD_SET_CMD | TEXCOORD_SET(unit) |
-		 ENABLE_TEXCOORD_PARAMS | TEXCOORDS_ARE_NORMAL |
-		 TEXCOORDTYPE_CARTESIAN | ENABLE_ADDR_V_CNTL |
-		 TEXCOORD_ADDR_V_MODE(wrap_mode) |
-		 ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(wrap_mode));
+	BEGIN_BATCH(10);
+	OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
+	OUT_BATCH((offset & TM0S0_ADDRESS_MASK) | TM0S0_USE_FENCE);
+	OUT_BATCH(((pPix->drawable.height - 1) << TM0S1_HEIGHT_SHIFT) |
+		  ((pPix->drawable.width - 1) << TM0S1_WIDTH_SHIFT) | format);
+	OUT_BATCH((pitch/4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
+	OUT_BATCH(filter);
+	OUT_BATCH(0); /* default color */
+	OUT_BATCH(_3DSTATE_MAP_COORD_SET_CMD | TEXCOORD_SET(unit) |
+		  ENABLE_TEXCOORD_PARAMS | TEXCOORDS_ARE_NORMAL |
+		  TEXCOORDTYPE_CARTESIAN | ENABLE_ADDR_V_CNTL |
+		  TEXCOORD_ADDR_V_MODE(wrap_mode) |
+		  ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(wrap_mode));
 	/* map texel stream */
-	OUT_RING(_3DSTATE_MAP_COORD_SETBIND_CMD);
+	OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
 	if (unit == 0)
-	    OUT_RING(TEXBIND_SET0(TEXCOORDSRC_VTXSET_0) |
-		    TEXBIND_SET1(TEXCOORDSRC_KEEP) |
-		    TEXBIND_SET2(TEXCOORDSRC_KEEP) |
-		    TEXBIND_SET3(TEXCOORDSRC_KEEP));
+	    OUT_BATCH(TEXBIND_SET0(TEXCOORDSRC_VTXSET_0) |
+		      TEXBIND_SET1(TEXCOORDSRC_KEEP) |
+		      TEXBIND_SET2(TEXCOORDSRC_KEEP) |
+		      TEXBIND_SET3(TEXCOORDSRC_KEEP));
 	else
-	    OUT_RING(TEXBIND_SET0(TEXCOORDSRC_VTXSET_0) |
-		    TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
-		    TEXBIND_SET2(TEXCOORDSRC_KEEP) |
-		    TEXBIND_SET3(TEXCOORDSRC_KEEP));
-	OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD | (unit << 16) |
-		DISABLE_TEX_STREAM_BUMP | 
-		ENABLE_TEX_STREAM_COORD_SET |
-		TEX_STREAM_COORD_SET(unit) |
-		ENABLE_TEX_STREAM_MAP_IDX |
-		TEX_STREAM_MAP_IDX(unit));
-	ADVANCE_LP_RING();
+	    OUT_BATCH(TEXBIND_SET0(TEXCOORDSRC_VTXSET_0) |
+		      TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
+		      TEXBIND_SET2(TEXCOORDSRC_KEEP) |
+		      TEXBIND_SET3(TEXCOORDSRC_KEEP));
+	OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | (unit << 16) |
+		  DISABLE_TEX_STREAM_BUMP |
+		  ENABLE_TEX_STREAM_COORD_SET |
+		  TEX_STREAM_COORD_SET(unit) |
+		  ENABLE_TEX_STREAM_MAP_IDX |
+		  TEX_STREAM_MAP_IDX(unit));
+	ADVANCE_BATCH();
      }
 
 #ifdef I830DEBUG
@@ -418,43 +418,43 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
     {
 	uint32_t cblend, ablend, blendctl, vf2;
 
-	BEGIN_LP_RING(30);
+	BEGIN_BATCH(30);
 
 	/* color buffer */
-	OUT_RING(_3DSTATE_BUF_INFO_CMD);
-	OUT_RING(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE |
-			BUF_3D_PITCH(dst_pitch));
-	OUT_RING(BUF_3D_ADDR(dst_offset));
-	OUT_RING(MI_NOOP);
+	OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
+	OUT_BATCH(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE |
+		  BUF_3D_PITCH(dst_pitch));
+	OUT_BATCH(BUF_3D_ADDR(dst_offset));
+	OUT_BATCH(MI_NOOP);
 
-	OUT_RING(_3DSTATE_DST_BUF_VARS_CMD);
-	OUT_RING(dst_format);
+	OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
+	OUT_BATCH(dst_format);
 
 	/* defaults */
-	OUT_RING(_3DSTATE_DFLT_Z_CMD);
-	OUT_RING(0);
+	OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
+	OUT_BATCH(0);
 
-	OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
-	OUT_RING(0);
+	OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
+	OUT_BATCH(0);
 
-	OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
-	OUT_RING(0);
+	OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
+	OUT_BATCH(0);
 
-	OUT_RING(_3DSTATE_DRAW_RECT_CMD);
-	OUT_RING(0);
-	OUT_RING(0); /* ymin, xmin */
-	OUT_RING(DRAW_YMAX(pDst->drawable.height - 1) |
-		DRAW_XMAX(pDst->drawable.width - 1));
-	OUT_RING(0); /* yorig, xorig */
+	OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
+	OUT_BATCH(0);
+	OUT_BATCH(0); /* ymin, xmin */
+	OUT_BATCH(DRAW_YMAX(pDst->drawable.height - 1) |
+		  DRAW_XMAX(pDst->drawable.width - 1));
+	OUT_BATCH(0); /* yorig, xorig */
 
-	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) | 
-		I1_LOAD_S(3) | 1);
+	OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
+		  I1_LOAD_S(3) | 1);
 	if (pMask)
 	    vf2 = 2 << 12; /* 2 texture coord sets */
 	else
 	    vf2 = 1 << 12;
-	OUT_RING(vf2); /* TEXCOORDFMT_2D */
-	OUT_RING(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
+	OUT_BATCH(vf2); /* TEXCOORDFMT_2D */
+	OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
 
 	/* If component alpha is active in the mask and the blend operation
 	 * uses the source alpha, then we know we don't need the source
@@ -523,29 +523,29 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
 	    ablend |= TB0A_ARG2_SEL_ONE;
 	}
 
-	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
-		 LOAD_TEXTURE_BLEND_STAGE(0)|1);
-	OUT_RING(cblend);
-	OUT_RING(ablend);
-	OUT_RING(0);
+	OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
+		  LOAD_TEXTURE_BLEND_STAGE(0)|1);
+	OUT_BATCH(cblend);
+	OUT_BATCH(ablend);
+	OUT_BATCH(0);
 
 	blendctl = i830_get_blend_cntl(op, pMaskPicture, pDstPicture->format);
-	OUT_RING(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
-	OUT_RING(MI_NOOP);
-	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
-	OUT_RING(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | blendctl | 
-		 S8_ENABLE_COLOR_BUFFER_WRITE);
-
-	OUT_RING(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP | 
-		DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS | 
-		DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST | 
-		ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
+	OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
+	OUT_BATCH(MI_NOOP);
+	OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
+	OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | blendctl |
+		  S8_ENABLE_COLOR_BUFFER_WRITE);
+
+	OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
+		  DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
+		  DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
+		  ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
 	/* We have to explicitly say we don't want write disabled */
-	OUT_RING(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
-		DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
-		DISABLE_DITHER | ENABLE_COLOR_WRITE |
-		DISABLE_DEPTH_WRITE);
-	ADVANCE_LP_RING();
+	OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
+		  DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
+		  DISABLE_DITHER | ENABLE_COLOR_WRITE |
+		  DISABLE_DEPTH_WRITE);
+	ADVANCE_BATCH();
     }
 
 #ifdef I830DEBUG
@@ -604,43 +604,43 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
 	else
 		vertex_count = 3*4;
 
-	BEGIN_LP_RING(6+vertex_count);
+	BEGIN_BATCH(6+vertex_count);
 
-	OUT_RING(MI_NOOP);
-	OUT_RING(MI_NOOP);
-	OUT_RING(MI_NOOP);
-	OUT_RING(MI_NOOP);
-	OUT_RING(MI_NOOP);
+	OUT_BATCH(MI_NOOP);
+	OUT_BATCH(MI_NOOP);
+	OUT_BATCH(MI_NOOP);
+	OUT_BATCH(MI_NOOP);
+	OUT_BATCH(MI_NOOP);
 
-	OUT_RING(PRIM3D_INLINE | PRIM3D_RECTLIST | (vertex_count-1));
+	OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (vertex_count-1));
 
-	OUT_RING_F(-0.125 + dstX + w);
-	OUT_RING_F(-0.125 + dstY + h);
-	OUT_RING_F(src_x[2] / pI830->scale_units[0][0]);
-	OUT_RING_F(src_y[2] / pI830->scale_units[0][1]);
+	OUT_BATCH_F(-0.125 + dstX + w);
+	OUT_BATCH_F(-0.125 + dstY + h);
+	OUT_BATCH_F(src_x[2] / pI830->scale_units[0][0]);
+	OUT_BATCH_F(src_y[2] / pI830->scale_units[0][1]);
 	if (has_mask) {
-	    OUT_RING_F(mask_x[2] / pI830->scale_units[1][0]);
-	    OUT_RING_F(mask_y[2] / pI830->scale_units[1][1]);
+	    OUT_BATCH_F(mask_x[2] / pI830->scale_units[1][0]);
+	    OUT_BATCH_F(mask_y[2] / pI830->scale_units[1][1]);
 	}
 
-	OUT_RING_F(-0.125 + dstX);
-	OUT_RING_F(-0.125 + dstY + h);
-	OUT_RING_F(src_x[1] / pI830->scale_units[0][0]);
-	OUT_RING_F(src_y[1] / pI830->scale_units[0][1]);
+	OUT_BATCH_F(-0.125 + dstX);
+	OUT_BATCH_F(-0.125 + dstY + h);
+	OUT_BATCH_F(src_x[1] / pI830->scale_units[0][0]);
+	OUT_BATCH_F(src_y[1] / pI830->scale_units[0][1]);
 	if (has_mask) {
-	    OUT_RING_F(mask_x[1] / pI830->scale_units[1][0]);
-	    OUT_RING_F(mask_y[1] / pI830->scale_units[1][1]);
+	    OUT_BATCH_F(mask_x[1] / pI830->scale_units[1][0]);
+	    OUT_BATCH_F(mask_y[1] / pI830->scale_units[1][1]);
 	}
 
-	OUT_RING_F(-0.125 + dstX);
-	OUT_RING_F(-0.125 + dstY);
-	OUT_RING_F(src_x[0] / pI830->scale_units[0][0]);
-	OUT_RING_F(src_y[0] / pI830->scale_units[0][1]);
+	OUT_BATCH_F(-0.125 + dstX);
+	OUT_BATCH_F(-0.125 + dstY);
+	OUT_BATCH_F(src_x[0] / pI830->scale_units[0][0]);
+	OUT_BATCH_F(src_y[0] / pI830->scale_units[0][1]);
 	if (has_mask) {
-	    OUT_RING_F(mask_x[0] / pI830->scale_units[1][0]);
-	    OUT_RING_F(mask_y[0] / pI830->scale_units[1][1]);
+	    OUT_BATCH_F(mask_x[0] / pI830->scale_units[1][0]);
+	    OUT_BATCH_F(mask_y[0] / pI830->scale_units[1][1]);
 	}
-	ADVANCE_LP_RING();
+	ADVANCE_BATCH();
     }
 }
 
diff --git a/src/i830_ring.h b/src/i830_ring.h
index 177b0d52..cf789eb6 100644
--- a/src/i830_ring.h
+++ b/src/i830_ring.h
@@ -42,28 +42,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
     pI830->ring_next &= pI830->LpRing->tail_mask;			\
 } while (0)
 
-/** Copies a given number of bytes to the ring */
-#define OUT_RING_COPY(n, ptr) do {					\
-    if (I810_DEBUG & DEBUG_VERBOSE_RING)				\
-	ErrorF("OUT_RING_DATA %d bytes\n", n);				\
-    memcpy_volatile(pI830->LpRing->virtual_start + pI830->ring_next,	\
-		    ptr, n);						\
-    pI830->ring_used += n;						\
-    pI830->ring_next += n;						\
-    pI830->ring_next &= pI830->LpRing->tail_mask;			\
-} while (0)
-
-/** Pads the ring with a given number of zero bytes */
-#define OUT_RING_PAD(n) do {						\
-    if (I810_DEBUG & DEBUG_VERBOSE_RING)				\
-	ErrorF("OUT_RING_PAD %d bytes\n", n);				\
-    memset_volatile(pI830->LpRing->virtual_start + pI830->ring_next,	\
-		    0, n);						\
-    pI830->ring_used += n;						\
-    pI830->ring_next += n;						\
-    pI830->ring_next &= pI830->LpRing->tail_mask;			\
-} while (0)
-
 union intfloat {
 	float f;
 	unsigned int ui;
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 9a89cc9b..d72b9130 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -1146,6 +1146,18 @@ i830_sdvo_destroy (xf86OutputPtr output)
     }
 }
 
+static xf86CrtcPtr
+i830_sdvo_get_crtc(xf86OutputPtr output)
+{
+    ScrnInfoPtr	pScrn = output->scrn;
+    I830Ptr pI830 = I830PTR(pScrn);
+    I830OutputPrivatePtr intel_output = output->driver_private;
+    struct i830_sdvo_priv *dev_priv = intel_output->dev_priv;
+    int pipe = !!(INREG(dev_priv->output_device) & SDVO_PIPE_B_SELECT);
+   
+    return i830_pipe_to_crtc(pScrn, pipe);
+}
+
 static const xf86OutputFuncsRec i830_sdvo_output_funcs = {
     .dpms = i830_sdvo_dpms,
     .save = i830_sdvo_save,
@@ -1157,7 +1169,10 @@ static const xf86OutputFuncsRec i830_sdvo_output_funcs = {
     .commit = i830_output_commit,
     .detect = i830_sdvo_detect,
     .get_modes = i830_sdvo_get_modes,
-    .destroy = i830_sdvo_destroy
+    .destroy = i830_sdvo_destroy,
+#ifdef RANDR_GET_CRTC_INTERFACE
+    .get_crtc = i830_sdvo_get_crtc,
+#endif
 };
 
 void
diff --git a/src/i830_tv.c b/src/i830_tv.c
index 095f59bd..b478cc7d 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -1640,6 +1640,16 @@ i830_tv_set_property(xf86OutputPtr output, Atom property,
 }
 #endif /* RANDR_12_INTERFACE */
 
+static xf86CrtcPtr
+i830_tv_get_crtc(xf86OutputPtr output)
+{
+    ScrnInfoPtr	pScrn = output->scrn;
+    I830Ptr pI830 = I830PTR(pScrn);
+    int pipe = !!(INREG(TV_CTL) & TV_ENC_PIPEB_SELECT);
+   
+    return i830_pipe_to_crtc(pScrn, pipe);
+}
+
 static const xf86OutputFuncsRec i830_tv_output_funcs = {
     .create_resources = i830_tv_create_resources,
     .dpms = i830_tv_dpms,
@@ -1656,6 +1666,9 @@ static const xf86OutputFuncsRec i830_tv_output_funcs = {
 #ifdef RANDR_12_INTERFACE
     .set_property = i830_tv_set_property,
 #endif
+#ifdef RANDR_GET_CRTC_INTERFACE
+    .get_crtc = i830_tv_get_crtc,
+#endif
 };
 
 void
diff --git a/src/i830_video.c b/src/i830_video.c
index cc351f1c..c25e9921 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -421,18 +421,18 @@ i830_overlay_on(ScrnInfoPtr pScrn)
 	deactivate = i830_pipe_a_require_activate (pScrn);
 
     overlay->OCMD &= ~OVERLAY_ENABLE;
-    BEGIN_LP_RING(6);
-    OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
-    OUT_RING(MI_NOOP);
-    OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_ON);
+    BEGIN_BATCH(6);
+    OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE);
+    OUT_BATCH(MI_NOOP);
+    OUT_BATCH(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_ON);
     if (OVERLAY_NOPHYSICAL(pI830))
-	OUT_RING(pI830->overlay_regs->offset | OFC_UPDATE);
+	OUT_BATCH(pI830->overlay_regs->offset | OFC_UPDATE);
     else
-	OUT_RING(pI830->overlay_regs->bus_addr | OFC_UPDATE);
+	OUT_BATCH(pI830->overlay_regs->bus_addr | OFC_UPDATE);
     /* Wait for the overlay to light up before attempting to use it */
-    OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
-    OUT_RING(MI_NOOP);
-    ADVANCE_LP_RING();
+    OUT_BATCH(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+    OUT_BATCH(MI_NOOP);
+    ADVANCE_BATCH();
     i830WaitSync(pScrn);
     
     /*
@@ -466,12 +466,12 @@ i830_overlay_continue(ScrnInfoPtr pScrn, Bool update_filter)
 	flip_addr |= OFC_UPDATE;
     OVERLAY_DEBUG ("overlay_continue cmd 0x%08x  -> 0x%08x sta 0x%08x\n",
 		   overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
-    BEGIN_LP_RING(4);
-    OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
-    OUT_RING(MI_NOOP);
-    OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_CONTINUE);
-    OUT_RING(flip_addr);
-    ADVANCE_LP_RING();
+    BEGIN_BATCH(4);
+    OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE);
+    OUT_BATCH(MI_NOOP);
+    OUT_BATCH(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_CONTINUE);
+    OUT_BATCH(flip_addr);
+    ADVANCE_BATCH();
     OVERLAY_DEBUG("overlay_continue\n");
 }
 
@@ -492,10 +492,10 @@ i830_overlay_off(ScrnInfoPtr pScrn)
      * executed
      */
     {
-	BEGIN_LP_RING(2);
-	OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
-	OUT_RING(MI_NOOP);
-	ADVANCE_LP_RING();
+	BEGIN_BATCH(2);
+	OUT_BATCH(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+	OUT_BATCH(MI_NOOP);
+	ADVANCE_BATCH();
 	i830WaitSync(pScrn);
     }
     
@@ -506,17 +506,17 @@ i830_overlay_off(ScrnInfoPtr pScrn)
 	overlay->OCMD &= ~OVERLAY_ENABLE;
 	OVERLAY_DEBUG ("overlay_off cmd 0x%08x -> 0x%08x sta 0x%08x\n",
 		       overlay->OCMD, INREG(OCMD_REGISTER), INREG(DOVSTA));
-	BEGIN_LP_RING(6);
-	OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
-	OUT_RING(MI_NOOP);
-	OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_CONTINUE);
+	BEGIN_BATCH(6);
+	OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE);
+	OUT_BATCH(MI_NOOP);
+	OUT_BATCH(MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_CONTINUE);
 	if (OVERLAY_NOPHYSICAL(pI830))
-	    OUT_RING(pI830->overlay_regs->offset);
+	    OUT_BATCH(pI830->overlay_regs->offset);
 	else
-	    OUT_RING(pI830->overlay_regs->bus_addr);
-	OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
-	OUT_RING(MI_NOOP);
-	ADVANCE_LP_RING();
+	    OUT_BATCH(pI830->overlay_regs->bus_addr);
+	OUT_BATCH(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+	OUT_BATCH(MI_NOOP);
+	ADVANCE_BATCH();
 	i830WaitSync(pScrn);
     }
     *pI830->overlayOn = FALSE;
diff --git a/src/i830_xaa.c b/src/i830_xaa.c
index fabac20e..0df7f98e 100644
--- a/src/i830_xaa.c
+++ b/src/i830_xaa.c
@@ -352,22 +352,22 @@ I830SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y, int w, int h)
 	ErrorF("I830SubsequentFillRectSolid %d,%d %dx%d\n", x, y, w, h);
 
     {
-	BEGIN_LP_RING(6);
+	BEGIN_BATCH(6);
 
 	if (pScrn->bitsPerPixel == 32) {
-	    OUT_RING(COLOR_BLT_CMD | COLOR_BLT_WRITE_ALPHA |
-		     COLOR_BLT_WRITE_RGB);
+	    OUT_BATCH(COLOR_BLT_CMD | COLOR_BLT_WRITE_ALPHA |
+		      COLOR_BLT_WRITE_RGB);
 	} else {
-	    OUT_RING(COLOR_BLT_CMD);
+	    OUT_BATCH(COLOR_BLT_CMD);
 	}
-	OUT_RING(pI830->BR[13]);
-	OUT_RING((h << 16) | (w * pI830->cpp));
-	OUT_RING(pI830->bufferOffset + (y * pScrn->displayWidth + x) *
-		 pI830->cpp);
-	OUT_RING(pI830->BR[16]);
-	OUT_RING(0);
-
-	ADVANCE_LP_RING();
+	OUT_BATCH(pI830->BR[13]);
+	OUT_BATCH((h << 16) | (w * pI830->cpp));
+	OUT_BATCH(pI830->bufferOffset + (y * pScrn->displayWidth + x) *
+		  pI830->cpp);
+	OUT_BATCH(pI830->BR[16]);
+	OUT_BATCH(0);
+
+	ADVANCE_BATCH();
     }
 
     if (IS_I965G(pI830))
@@ -429,23 +429,23 @@ I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int src_x1, int src_y1,
     dst_y2 = dst_y1 + h;
 
     {
-	BEGIN_LP_RING(8);
+	BEGIN_BATCH(8);
 
 	if (pScrn->bitsPerPixel == 32) {
-	    OUT_RING(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
-		     XY_SRC_COPY_BLT_WRITE_RGB | tiled << 15 | tiled << 11);
+	    OUT_BATCH(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
+		      XY_SRC_COPY_BLT_WRITE_RGB | tiled << 15 | tiled << 11);
 	} else {
-	    OUT_RING(XY_SRC_COPY_BLT_CMD | tiled << 15 | tiled << 11);
+	    OUT_BATCH(XY_SRC_COPY_BLT_CMD | tiled << 15 | tiled << 11);
 	}
-	OUT_RING(pI830->BR[13]);
-	OUT_RING((dst_y1 << 16) | (dst_x1 & 0xffff));
-	OUT_RING((dst_y2 << 16) | (dst_x2 & 0xffff));
-	OUT_RING(pI830->bufferOffset);
-	OUT_RING((src_y1 << 16) | (src_x1 & 0xffff));
-	OUT_RING(pI830->BR[13] & 0xFFFF);
-	OUT_RING(pI830->bufferOffset);
-
-	ADVANCE_LP_RING();
+	OUT_BATCH(pI830->BR[13]);
+	OUT_BATCH((dst_y1 << 16) | (dst_x1 & 0xffff));
+	OUT_BATCH((dst_y2 << 16) | (dst_x2 & 0xffff));
+	OUT_BATCH(pI830->bufferOffset);
+	OUT_BATCH((src_y1 << 16) | (src_x1 & 0xffff));
+	OUT_BATCH(pI830->BR[13] & 0xFFFF);
+	OUT_BATCH(pI830->bufferOffset);
+
+	ADVANCE_BATCH();
     }
 
     if (IS_I965G(pI830))
@@ -506,28 +506,28 @@ I830SubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn, int pattx, int patty,
 	ErrorF("I830SubsequentMono8x8PatternFillRect\n");
 
     {
-	BEGIN_LP_RING(10);
+	BEGIN_BATCH(10);
 
 	if (pScrn->bitsPerPixel == 32) {
-	    OUT_RING(XY_MONO_PAT_BLT_CMD | XY_MONO_PAT_BLT_WRITE_ALPHA |
-		     XY_MONO_PAT_BLT_WRITE_RGB | tiled << 11 |
-		     ((patty << 8) & XY_MONO_PAT_VERT_SEED) |
-		     ((pattx << 12) & XY_MONO_PAT_HORT_SEED));
+	    OUT_BATCH(XY_MONO_PAT_BLT_CMD | XY_MONO_PAT_BLT_WRITE_ALPHA |
+		      XY_MONO_PAT_BLT_WRITE_RGB | tiled << 11 |
+		      ((patty << 8) & XY_MONO_PAT_VERT_SEED) |
+		      ((pattx << 12) & XY_MONO_PAT_HORT_SEED));
 	} else {
-	    OUT_RING(XY_MONO_PAT_BLT_CMD | tiled << 11 |
-		     ((patty << 8) & XY_MONO_PAT_VERT_SEED) |
-		     ((pattx << 12) & XY_MONO_PAT_HORT_SEED));
+	    OUT_BATCH(XY_MONO_PAT_BLT_CMD | tiled << 11 |
+		      ((patty << 8) & XY_MONO_PAT_VERT_SEED) |
+		      ((pattx << 12) & XY_MONO_PAT_HORT_SEED));
 	}
-	OUT_RING(pI830->BR[13]);
-	OUT_RING((y1 << 16) | x1);
-	OUT_RING((y2 << 16) | x2);
-	OUT_RING(pI830->bufferOffset);
-	OUT_RING(pI830->BR[18]);		/* bg */
-	OUT_RING(pI830->BR[19]);		/* fg */
-	OUT_RING(pI830->BR[16]);		/* pattern data */
-	OUT_RING(pI830->BR[17]);
-	OUT_RING(0);
-	ADVANCE_LP_RING();
+	OUT_BATCH(pI830->BR[13]);
+	OUT_BATCH((y1 << 16) | x1);
+	OUT_BATCH((y2 << 16) | x2);
+	OUT_BATCH(pI830->bufferOffset);
+	OUT_BATCH(pI830->BR[18]);		/* bg */
+	OUT_BATCH(pI830->BR[19]);		/* fg */
+	OUT_BATCH(pI830->BR[16]);		/* pattern data */
+	OUT_BATCH(pI830->BR[17]);
+	OUT_BATCH(0);
+	ADVANCE_BATCH();
     }
 
     if (IS_I965G(pI830))
@@ -630,23 +630,23 @@ I830SubsequentColorExpandScanline(ScrnInfoPtr pScrn, int bufno)
 	       bufno, pI830->BR[12]);
 
     {
-	BEGIN_LP_RING(8);
+	BEGIN_BATCH(8);
 
 	if (pScrn->bitsPerPixel == 32) {
-	    OUT_RING(XY_MONO_SRC_BLT_CMD | XY_MONO_SRC_BLT_WRITE_ALPHA |
-		     tiled << 11 | XY_MONO_SRC_BLT_WRITE_RGB);
+	    OUT_BATCH(XY_MONO_SRC_BLT_CMD | XY_MONO_SRC_BLT_WRITE_ALPHA |
+		      tiled << 11 | XY_MONO_SRC_BLT_WRITE_RGB);
 	} else {
-	    OUT_RING(XY_MONO_SRC_BLT_CMD | tiled << 11);
+	    OUT_BATCH(XY_MONO_SRC_BLT_CMD | tiled << 11);
 	}
-	OUT_RING(pI830->BR[13]);
-	OUT_RING(0);			/* x1 = 0, y1 = 0 */
-	OUT_RING(pI830->BR[11]);		/* x2 = w, y2 = 1 */
-	OUT_RING(pI830->BR[9]);		/* dst addr */
-	OUT_RING(pI830->BR[12]);		/* src addr */
-	OUT_RING(pI830->BR[18]);		/* bg */
-	OUT_RING(pI830->BR[19]);		/* fg */
-
-	ADVANCE_LP_RING();
+	OUT_BATCH(pI830->BR[13]);
+	OUT_BATCH(0);			/* x1 = 0, y1 = 0 */
+	OUT_BATCH(pI830->BR[11]);		/* x2 = w, y2 = 1 */
+	OUT_BATCH(pI830->BR[9]);		/* dst addr */
+	OUT_BATCH(pI830->BR[12]);		/* src addr */
+	OUT_BATCH(pI830->BR[18]);		/* bg */
+	OUT_BATCH(pI830->BR[19]);		/* fg */
+
+	ADVANCE_BATCH();
     }
 
     /* Advance to next scanline.
@@ -730,23 +730,23 @@ I830SubsequentImageWriteScanline(ScrnInfoPtr pScrn, int bufno)
 	       bufno, pI830->BR[12]);
 
     {
-	BEGIN_LP_RING(8);
+	BEGIN_BATCH(8);
 
 	if (pScrn->bitsPerPixel == 32) {
-	    OUT_RING(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
-		     tiled << 11 | XY_SRC_COPY_BLT_WRITE_RGB);
+	    OUT_BATCH(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
+		      tiled << 11 | XY_SRC_COPY_BLT_WRITE_RGB);
 	} else {
-	    OUT_RING(XY_SRC_COPY_BLT_CMD | tiled << 11);
+	    OUT_BATCH(XY_SRC_COPY_BLT_CMD | tiled << 11);
 	}
-	OUT_RING(pI830->BR[13]);
-	OUT_RING(0);				/* x1 = 0, y1 = 0 */
-	OUT_RING(pI830->BR[11]);		/* x2 = w, y2 = 1 */
-	OUT_RING(pI830->BR[9]);			/* dst addr */
-	OUT_RING(0);				/* source origin (0,0) */
-	OUT_RING(pI830->BR[11] & 0xffff);	/* source pitch */
-	OUT_RING(pI830->BR[12]);		/* src addr */
-
-	ADVANCE_LP_RING();
+	OUT_BATCH(pI830->BR[13]);
+	OUT_BATCH(0);				/* x1 = 0, y1 = 0 */
+	OUT_BATCH(pI830->BR[11]);		/* x2 = w, y2 = 1 */
+	OUT_BATCH(pI830->BR[9]);			/* dst addr */
+	OUT_BATCH(0);				/* source origin (0,0) */
+	OUT_BATCH(pI830->BR[11] & 0xffff);	/* source pitch */
+	OUT_BATCH(pI830->BR[12]);		/* src addr */
+
+	ADVANCE_BATCH();
     }
 
     /* Advance to next scanline.
diff --git a/src/i915_3d.c b/src/i915_3d.c
index ff591716..b2dbeed4 100644
--- a/src/i915_3d.c
+++ b/src/i915_3d.c
@@ -38,32 +38,32 @@ void I915EmitInvarientState( ScrnInfoPtr pScrn )
 {
    I830Ptr pI830 = I830PTR(pScrn);
 
-   BEGIN_LP_RING(24);
+   BEGIN_BATCH(24);
 
-   OUT_RING(_3DSTATE_AA_CMD |
+   OUT_BATCH(_3DSTATE_AA_CMD |
 	     AA_LINE_ECAAR_WIDTH_ENABLE |
 	     AA_LINE_ECAAR_WIDTH_1_0 |
 	     AA_LINE_REGION_WIDTH_ENABLE |
 	     AA_LINE_REGION_WIDTH_1_0);
 
    /* Disable independent alpha blend */
-   OUT_RING(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
-	    IAB_MODIFY_ENABLE |
-	    IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
-	    IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
-	    IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
+   OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
+	     IAB_MODIFY_ENABLE |
+	     IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
+	     IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
+	     IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
 
-   OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_DFLT_Z_CMD);
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
+   OUT_BATCH(0);
 
    /* Don't support texture crossbar yet */
-   OUT_RING(_3DSTATE_COORD_SET_BINDINGS |
+   OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 	     CSB_TCB(0, 0) |
 	     CSB_TCB(1, 1) |
 	     CSB_TCB(2, 2) |
@@ -73,7 +73,7 @@ void I915EmitInvarientState( ScrnInfoPtr pScrn )
 	     CSB_TCB(6, 6) |
 	     CSB_TCB(7, 7));
 
-   OUT_RING(_3DSTATE_RASTER_RULES_CMD |
+   OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 	     ENABLE_POINT_RASTER_RULE |
 	     OGL_POINT_RASTER_RULE |
 	     ENABLE_LINE_STRIP_PROVOKE_VRTX |
@@ -83,29 +83,29 @@ void I915EmitInvarientState( ScrnInfoPtr pScrn )
 	     ENABLE_TEXKILL_3D_4D |
 	     TEXKILL_4D);
 
-   OUT_RING(_3DSTATE_MODES_4_CMD |
-	    ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
-	    ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
-	    ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
+   OUT_BATCH(_3DSTATE_MODES_4_CMD |
+	     ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
+	     ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
+	     ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
 
-   OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 0);
-   OUT_RING(0x00000000);	/* Disable texture coordinate wrap-shortest */
+   OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 0);
+   OUT_BATCH(0x00000000);	/* Disable texture coordinate wrap-shortest */
 
-   OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
-   OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD);
-   OUT_RING(0);
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
+   OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_DEPTH_SUBRECT_DISABLE);
+   OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 
-   OUT_RING(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
-   OUT_RING(0);
+   OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
+   OUT_BATCH(0);
 
-   OUT_RING(_3DSTATE_STIPPLE);
-   OUT_RING(0x00000000);
+   OUT_BATCH(_3DSTATE_STIPPLE);
+   OUT_BATCH(0x00000000);
 
-   OUT_RING(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0 );
-   OUT_RING(MI_NOOP);
+   OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0 );
+   OUT_BATCH(MI_NOOP);
 
-   ADVANCE_LP_RING();
+   ADVANCE_BATCH();
 }
diff --git a/src/i915_render.c b/src/i915_render.c
index 7c45c807..fe02e631 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -341,54 +341,54 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
     }
 
     if (pMask == NULL) {
-	BEGIN_LP_RING(10);
-	OUT_RING(_3DSTATE_MAP_STATE | 3);
-	OUT_RING(0x00000001); /* map 0 */
-	OUT_RING(pI830->mapstate[0]);
-	OUT_RING(pI830->mapstate[1]);
-	OUT_RING(pI830->mapstate[2]);
-
-	OUT_RING(_3DSTATE_SAMPLER_STATE | 3);
-	OUT_RING(0x00000001); /* sampler 0 */
-	OUT_RING(pI830->samplerstate[0]);
-	OUT_RING(pI830->samplerstate[1]);
-	OUT_RING(pI830->samplerstate[2]);
-	ADVANCE_LP_RING();
+	BEGIN_BATCH(10);
+	OUT_BATCH(_3DSTATE_MAP_STATE | 3);
+	OUT_BATCH(0x00000001); /* map 0 */
+	OUT_BATCH(pI830->mapstate[0]);
+	OUT_BATCH(pI830->mapstate[1]);
+	OUT_BATCH(pI830->mapstate[2]);
+
+	OUT_BATCH(_3DSTATE_SAMPLER_STATE | 3);
+	OUT_BATCH(0x00000001); /* sampler 0 */
+	OUT_BATCH(pI830->samplerstate[0]);
+	OUT_BATCH(pI830->samplerstate[1]);
+	OUT_BATCH(pI830->samplerstate[2]);
+	ADVANCE_BATCH();
     } else {
-	BEGIN_LP_RING(16);
-	OUT_RING(_3DSTATE_MAP_STATE | 6);
-	OUT_RING(0x00000003); /* map 0,1 */
-	OUT_RING(pI830->mapstate[0]);
-	OUT_RING(pI830->mapstate[1]);
-	OUT_RING(pI830->mapstate[2]);
-	OUT_RING(pI830->mapstate[3]);
-	OUT_RING(pI830->mapstate[4]);
-	OUT_RING(pI830->mapstate[5]);
-
-	OUT_RING(_3DSTATE_SAMPLER_STATE | 6);
-	OUT_RING(0x00000003); /* sampler 0,1 */
-	OUT_RING(pI830->samplerstate[0]);
-	OUT_RING(pI830->samplerstate[1]);
-	OUT_RING(pI830->samplerstate[2]);
-	OUT_RING(pI830->samplerstate[3]);
-	OUT_RING(pI830->samplerstate[4]);
-	OUT_RING(pI830->samplerstate[5]);
-	ADVANCE_LP_RING();
+	BEGIN_BATCH(16);
+	OUT_BATCH(_3DSTATE_MAP_STATE | 6);
+	OUT_BATCH(0x00000003); /* map 0,1 */
+	OUT_BATCH(pI830->mapstate[0]);
+	OUT_BATCH(pI830->mapstate[1]);
+	OUT_BATCH(pI830->mapstate[2]);
+	OUT_BATCH(pI830->mapstate[3]);
+	OUT_BATCH(pI830->mapstate[4]);
+	OUT_BATCH(pI830->mapstate[5]);
+
+	OUT_BATCH(_3DSTATE_SAMPLER_STATE | 6);
+	OUT_BATCH(0x00000003); /* sampler 0,1 */
+	OUT_BATCH(pI830->samplerstate[0]);
+	OUT_BATCH(pI830->samplerstate[1]);
+	OUT_BATCH(pI830->samplerstate[2]);
+	OUT_BATCH(pI830->samplerstate[3]);
+	OUT_BATCH(pI830->samplerstate[4]);
+	OUT_BATCH(pI830->samplerstate[5]);
+	ADVANCE_BATCH();
     }
     {
 	uint32_t ss2;
 
-	BEGIN_LP_RING(16);
-	OUT_RING(_3DSTATE_BUF_INFO_CMD);
-	OUT_RING(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE|
-		BUF_3D_PITCH(dst_pitch));
-	OUT_RING(BUF_3D_ADDR(dst_offset));
+	BEGIN_BATCH(16);
+	OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
+	OUT_BATCH(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE|
+		  BUF_3D_PITCH(dst_pitch));
+	OUT_BATCH(BUF_3D_ADDR(dst_offset));
 
-	OUT_RING(_3DSTATE_DST_BUF_VARS_CMD);
-	OUT_RING(dst_format);
+	OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
+	OUT_BATCH(dst_format);
 
-	OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
-		 I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 3);
+	OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
+		  I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 3);
 	ss2 = S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D);
 	if (pMask)
 		ss2 |= S2_TEXCOORD_FMT(1, TEXCOORDFMT_2D);
@@ -400,23 +400,23 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
 	ss2 |= S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT);
 	ss2 |= S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT);
 	ss2 |= S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT);
-	OUT_RING(ss2);
-	OUT_RING((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
-		 S4_CULLMODE_NONE| S4_VFMT_XY);
+	OUT_BATCH(ss2);
+	OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
+		  S4_CULLMODE_NONE| S4_VFMT_XY);
 	blendctl = i915_get_blend_cntl(op, pMaskPicture, pDstPicture->format);
-	OUT_RING(0x00000000); /* Disable stencil buffer */
-	OUT_RING(S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
-		 (BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT) | blendctl);
+	OUT_BATCH(0x00000000); /* Disable stencil buffer */
+	OUT_BATCH(S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
+		  (BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT) | blendctl);
 
 	/* draw rect is unconditional */
-	OUT_RING(_3DSTATE_DRAW_RECT_CMD);
-	OUT_RING(0x00000000);
-	OUT_RING(0x00000000);  /* ymin, xmin*/
-	OUT_RING(DRAW_YMAX(pDst->drawable.height - 1) |
-		 DRAW_XMAX(pDst->drawable.width - 1));
-	OUT_RING(0x00000000);  /* yorig, xorig (relate to color buffer?)*/
-	OUT_RING(MI_NOOP);
-	ADVANCE_LP_RING();
+	OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
+	OUT_BATCH(0x00000000);
+	OUT_BATCH(0x00000000);  /* ymin, xmin*/
+	OUT_BATCH(DRAW_YMAX(pDst->drawable.height - 1) |
+		  DRAW_XMAX(pDst->drawable.width - 1));
+	OUT_BATCH(0x00000000);  /* yorig, xorig (relate to color buffer?)*/
+	OUT_BATCH(MI_NOOP);
+	ADVANCE_BATCH();
     }
 
     if (dst_format == COLR_BUF_8BIT)
diff --git a/src/i915_video.c b/src/i915_video.c
index 7416efcd..aeb37293 100644
--- a/src/i915_video.c
+++ b/src/i915_video.c
@@ -75,88 +75,90 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
    IntelEmitInvarientState(pScrn);
    *pI830->last_3d = LAST_3D_VIDEO;
 
-   BEGIN_LP_RING(20);
+   BEGIN_BATCH(20);
 
    /* flush map & render cache */
-   OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
-   OUT_RING(0x00000000);
+   OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
+   OUT_BATCH(0x00000000);
 
    /* draw rect -- just clipping */
-   OUT_RING(_3DSTATE_DRAW_RECT_CMD);
-   OUT_RING(DRAW_DITHER_OFS_X(pPixmap->drawable.x & 3) |
-	    DRAW_DITHER_OFS_Y(pPixmap->drawable.y & 3));
-   OUT_RING(0x00000000);	/* ymin, xmin */
-   OUT_RING((pPixmap->drawable.width - 1) |
-	    (pPixmap->drawable.height - 1) << 16); /* ymax, xmax */
-   OUT_RING(0x00000000);	/* yorigin, xorigin */
-   OUT_RING(MI_NOOP);
-
-   OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
-	    I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 3);
-   OUT_RING(S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
-	    S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT) |
-	    S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
-	    S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
-	    S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
-	    S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
-	    S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
-	    S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT));
-   OUT_RING((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
-	    S4_CULLMODE_NONE | S4_VFMT_XY);
+   OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
+   OUT_BATCH(DRAW_DITHER_OFS_X(pPixmap->drawable.x & 3) |
+	     DRAW_DITHER_OFS_Y(pPixmap->drawable.y & 3));
+   OUT_BATCH(0x00000000);	/* ymin, xmin */
+   OUT_BATCH((pPixmap->drawable.width - 1) |
+	     (pPixmap->drawable.height - 1) << 16); /* ymax, xmax */
+   OUT_BATCH(0x00000000);	/* yorigin, xorigin */
+   OUT_BATCH(MI_NOOP);
+
+   OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
+	     I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 3);
+   OUT_BATCH(S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
+	     S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT) |
+	     S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
+	     S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
+	     S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
+	     S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
+	     S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
+	     S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT));
+   OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
+	     S4_CULLMODE_NONE | S4_VFMT_XY);
    s5 = 0x0;
    if (pI830->cpp == 2)
       s5 |= S5_COLOR_DITHER_ENABLE;
-   OUT_RING(s5); /* S5 - enable bits */
-   OUT_RING((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
-	    (2 << S6_CBUF_SRC_BLEND_FACT_SHIFT) |
-	    (1 << S6_CBUF_DST_BLEND_FACT_SHIFT) | S6_COLOR_WRITE_ENABLE |
-	    (2 << S6_TRISTRIP_PV_SHIFT));
+   OUT_BATCH(s5); /* S5 - enable bits */
+   OUT_BATCH((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
+	     (2 << S6_CBUF_SRC_BLEND_FACT_SHIFT) |
+	     (1 << S6_CBUF_DST_BLEND_FACT_SHIFT) | S6_COLOR_WRITE_ENABLE |
+	     (2 << S6_TRISTRIP_PV_SHIFT));
 
-   OUT_RING(_3DSTATE_CONST_BLEND_COLOR_CMD);
-   OUT_RING(0x00000000);
+   OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
+   OUT_BATCH(0x00000000);
 
-   OUT_RING(_3DSTATE_DST_BUF_VARS_CMD);
+   OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
    if (pI830->cpp == 2)
       format = COLR_BUF_RGB565;
    else
       format = COLR_BUF_ARGB8888 | DEPTH_FRMT_24_FIXED_8_OTHER;
 
-   OUT_RING(LOD_PRECLAMP_OGL |
-     DSTORG_HORT_BIAS(0x80) | DSTORG_VERT_BIAS(0x80) | format);
+   OUT_BATCH(LOD_PRECLAMP_OGL |
+	     DSTORG_HORT_BIAS(0x80) |
+	     DSTORG_VERT_BIAS(0x80) |
+	     format);
 
    /* front buffer, pitch, offset */
-   OUT_RING(_3DSTATE_BUF_INFO_CMD);
-   OUT_RING(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
-	    BUF_3D_PITCH(intel_get_pixmap_pitch(pPixmap)));
-   OUT_RING(BUF_3D_ADDR(intel_get_pixmap_offset(pPixmap)));
-   ADVANCE_LP_RING();
+   OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
+   OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
+	     BUF_3D_PITCH(intel_get_pixmap_pitch(pPixmap)));
+   OUT_BATCH(BUF_3D_ADDR(intel_get_pixmap_offset(pPixmap)));
+   ADVANCE_BATCH();
 
    if (!planar) {
       FS_LOCALS(10);
 
-      BEGIN_LP_RING(16);
-      OUT_RING(_3DSTATE_PIXEL_SHADER_CONSTANTS | 4);
-      OUT_RING(0x0000001);	/* constant 0 */
+      BEGIN_BATCH(16);
+      OUT_BATCH(_3DSTATE_PIXEL_SHADER_CONSTANTS | 4);
+      OUT_BATCH(0x0000001);	/* constant 0 */
       /* constant 0: brightness/contrast */
-      OUT_RING_F(pPriv->brightness / 128.0);
-      OUT_RING_F(pPriv->contrast / 255.0);
-      OUT_RING_F(0.0);
-      OUT_RING_F(0.0);
-
-      OUT_RING(_3DSTATE_SAMPLER_STATE | 3);
-      OUT_RING(0x00000001);
-      OUT_RING(SS2_COLORSPACE_CONVERSION |
-	       (FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
-	       (FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
-      OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
-	       (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
-	       (0 << SS3_TEXTUREMAP_INDEX_SHIFT) |
-	       SS3_NORMALIZED_COORDS);
-      OUT_RING(0x00000000);
-
-      OUT_RING(_3DSTATE_MAP_STATE | 3);
-      OUT_RING(0x00000001);	/* texture map #1 */
-      OUT_RING(pPriv->YBuf0offset);
+      OUT_BATCH_F(pPriv->brightness / 128.0);
+      OUT_BATCH_F(pPriv->contrast / 255.0);
+      OUT_BATCH_F(0.0);
+      OUT_BATCH_F(0.0);
+
+      OUT_BATCH(_3DSTATE_SAMPLER_STATE | 3);
+      OUT_BATCH(0x00000001);
+      OUT_BATCH(SS2_COLORSPACE_CONVERSION |
+		(FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
+		(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
+      OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
+		(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
+		(0 << SS3_TEXTUREMAP_INDEX_SHIFT) |
+		SS3_NORMALIZED_COORDS);
+      OUT_BATCH(0x00000000);
+
+      OUT_BATCH(_3DSTATE_MAP_STATE | 3);
+      OUT_BATCH(0x00000001);	/* texture map #1 */
+      OUT_BATCH(pPriv->YBuf0offset);
       ms3 = MAPSURF_422 | MS3_USE_FENCE_REGS;
       switch (id) {
       case FOURCC_YUY2:
@@ -168,10 +170,10 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
       }
       ms3 |= (height - 1) << MS3_HEIGHT_SHIFT;
       ms3 |= (width - 1) << MS3_WIDTH_SHIFT;
-      OUT_RING(ms3);
-      OUT_RING(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
+      OUT_BATCH(ms3);
+      OUT_BATCH(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
 
-      ADVANCE_LP_RING();
+      ADVANCE_BATCH();
 
       FS_BEGIN();
       i915_fs_dcl(FS_S0);
@@ -186,7 +188,7 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
    } else {
       FS_LOCALS(16);
 
-      BEGIN_LP_RING(22 + 11 + 11);
+      BEGIN_BATCH(22 + 11 + 11);
       /* For the planar formats, we set up three samplers -- one for each plane,
        * in a Y8 format.  Because I couldn't get the special PLANAR_TO_PACKED
        * shader setup to work, I did the manual pixel shader:
@@ -206,85 +208,85 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
        * r3 = (v,v,v,v)
        * OC = (r,g,b,1)
        */
-      OUT_RING(_3DSTATE_PIXEL_SHADER_CONSTANTS | (22 - 2));
-      OUT_RING(0x000001f);	/* constants 0-4 */
+      OUT_BATCH(_3DSTATE_PIXEL_SHADER_CONSTANTS | (22 - 2));
+      OUT_BATCH(0x000001f);	/* constants 0-4 */
       /* constant 0: normalization offsets */
-      OUT_RING_F(-0.0625);
-      OUT_RING_F(-0.5);
-      OUT_RING_F(-0.5);
-      OUT_RING_F(0.0);
+      OUT_BATCH_F(-0.0625);
+      OUT_BATCH_F(-0.5);
+      OUT_BATCH_F(-0.5);
+      OUT_BATCH_F(0.0);
       /* constant 1: r coefficients*/
-      OUT_RING_F(1.1643);
-      OUT_RING_F(0.0);
-      OUT_RING_F(1.5958);
-      OUT_RING_F(0.0);
+      OUT_BATCH_F(1.1643);
+      OUT_BATCH_F(0.0);
+      OUT_BATCH_F(1.5958);
+      OUT_BATCH_F(0.0);
       /* constant 2: g coefficients */
-      OUT_RING_F(1.1643);
-      OUT_RING_F(-0.39173);
-      OUT_RING_F(-0.81290);
-      OUT_RING_F(0.0);
+      OUT_BATCH_F(1.1643);
+      OUT_BATCH_F(-0.39173);
+      OUT_BATCH_F(-0.81290);
+      OUT_BATCH_F(0.0);
       /* constant 3: b coefficients */
-      OUT_RING_F(1.1643);
-      OUT_RING_F(2.017);
-      OUT_RING_F(0.0);
-      OUT_RING_F(0.0);
+      OUT_BATCH_F(1.1643);
+      OUT_BATCH_F(2.017);
+      OUT_BATCH_F(0.0);
+      OUT_BATCH_F(0.0);
       /* constant 4: brightness/contrast */
-      OUT_RING_F(pPriv->brightness / 128.0);
-      OUT_RING_F(pPriv->contrast / 255.0);
-      OUT_RING_F(0.0);
-      OUT_RING_F(0.0);
+      OUT_BATCH_F(pPriv->brightness / 128.0);
+      OUT_BATCH_F(pPriv->contrast / 255.0);
+      OUT_BATCH_F(0.0);
+      OUT_BATCH_F(0.0);
 
-      OUT_RING(_3DSTATE_SAMPLER_STATE | 9);
-      OUT_RING(0x00000007);
+      OUT_BATCH(_3DSTATE_SAMPLER_STATE | 9);
+      OUT_BATCH(0x00000007);
       /* sampler 0 */
-      OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
+      OUT_BATCH((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
 	       (FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
-      OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
+      OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
 	       (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
 	       (0 << SS3_TEXTUREMAP_INDEX_SHIFT) |
 	       SS3_NORMALIZED_COORDS);
-      OUT_RING(0x00000000);
+      OUT_BATCH(0x00000000);
       /* sampler 1 */
-      OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
+      OUT_BATCH((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
 	       (FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
-      OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
+      OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
 	       (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
 	       (1 << SS3_TEXTUREMAP_INDEX_SHIFT) |
 	       SS3_NORMALIZED_COORDS);
-      OUT_RING(0x00000000);
+      OUT_BATCH(0x00000000);
       /* sampler 2 */
-      OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
-	       (FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
-      OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
-	       (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
-	       (2 << SS3_TEXTUREMAP_INDEX_SHIFT) |
-	       SS3_NORMALIZED_COORDS);
-      OUT_RING(0x00000000);
-
-      OUT_RING(_3DSTATE_MAP_STATE | 9);
-      OUT_RING(0x00000007);
-
-      OUT_RING(pPriv->YBuf0offset);
+      OUT_BATCH((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
+		(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
+      OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
+		(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
+		(2 << SS3_TEXTUREMAP_INDEX_SHIFT) |
+		SS3_NORMALIZED_COORDS);
+      OUT_BATCH(0x00000000);
+
+      OUT_BATCH(_3DSTATE_MAP_STATE | 9);
+      OUT_BATCH(0x00000007);
+
+      OUT_BATCH(pPriv->YBuf0offset);
       ms3 = MAPSURF_8BIT | MT_8BIT_I8 | MS3_USE_FENCE_REGS;
       ms3 |= (height - 1) << MS3_HEIGHT_SHIFT;
       ms3 |= (width - 1) << MS3_WIDTH_SHIFT;
-      OUT_RING(ms3);
-      OUT_RING(((video_pitch * 2 / 4) - 1) << MS4_PITCH_SHIFT);
+      OUT_BATCH(ms3);
+      OUT_BATCH(((video_pitch * 2 / 4) - 1) << MS4_PITCH_SHIFT);
 
-      OUT_RING(pPriv->UBuf0offset);
+      OUT_BATCH(pPriv->UBuf0offset);
       ms3 = MAPSURF_8BIT | MT_8BIT_I8 | MS3_USE_FENCE_REGS;
       ms3 |= (height / 2 - 1) << MS3_HEIGHT_SHIFT;
       ms3 |= (width / 2 - 1) << MS3_WIDTH_SHIFT;
-      OUT_RING(ms3);
-      OUT_RING(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
+      OUT_BATCH(ms3);
+      OUT_BATCH(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
 
-      OUT_RING(pPriv->VBuf0offset);
+      OUT_BATCH(pPriv->VBuf0offset);
       ms3 = MAPSURF_8BIT | MT_8BIT_I8 | MS3_USE_FENCE_REGS;
       ms3 |= (height / 2 - 1) << MS3_HEIGHT_SHIFT;
       ms3 |= (width / 2 - 1) << MS3_WIDTH_SHIFT;
-      OUT_RING(ms3);
-      OUT_RING(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
-      ADVANCE_LP_RING();
+      OUT_BATCH(ms3);
+      OUT_BATCH(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
+      ADVANCE_BATCH();
 
       FS_BEGIN();
       /* Declare samplers */
@@ -334,10 +336,10 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
    }
    
    {
-      BEGIN_LP_RING(2);
-      OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
-      OUT_RING(0x00000000);
-      ADVANCE_LP_RING();
+      BEGIN_BATCH(2);
+      OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
+      OUT_BATCH(0x00000000);
+      ADVANCE_BATCH();
    }
 
    /* Set up the offset for translating from the given region (in screen
@@ -369,39 +371,39 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
       src_scale_x = ((float)src_w / width) / drw_w;
       src_scale_y  = ((float)src_h / height) / drw_h;
 
-      BEGIN_LP_RING(8 + 12);
-      OUT_RING(MI_NOOP);
-      OUT_RING(MI_NOOP);
-      OUT_RING(MI_NOOP);
-      OUT_RING(MI_NOOP);
-      OUT_RING(MI_NOOP);
-      OUT_RING(MI_NOOP);
-      OUT_RING(MI_NOOP);
+      BEGIN_BATCH(8 + 12);
+      OUT_BATCH(MI_NOOP);
+      OUT_BATCH(MI_NOOP);
+      OUT_BATCH(MI_NOOP);
+      OUT_BATCH(MI_NOOP);
+      OUT_BATCH(MI_NOOP);
+      OUT_BATCH(MI_NOOP);
+      OUT_BATCH(MI_NOOP);
 
       /* vertex data - rect list consists of bottom right, bottom left, and top
        * left vertices.
        */
-      OUT_RING(PRIM3D_INLINE | PRIM3D_RECTLIST | (12 - 1));
+      OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (12 - 1));
 
       /* bottom right */
-      OUT_RING_F(box_x2 + pix_xoff);
-      OUT_RING_F(box_y2 + pix_yoff);
-      OUT_RING_F((box_x2 - dxo) * src_scale_x);
-      OUT_RING_F((box_y2 - dyo) * src_scale_y);
+      OUT_BATCH_F(box_x2 + pix_xoff);
+      OUT_BATCH_F(box_y2 + pix_yoff);
+      OUT_BATCH_F((box_x2 - dxo) * src_scale_x);
+      OUT_BATCH_F((box_y2 - dyo) * src_scale_y);
 
       /* bottom left */
-      OUT_RING_F(box_x1 + pix_xoff);
-      OUT_RING_F(box_y2 + pix_yoff);
-      OUT_RING_F((box_x1 - dxo) * src_scale_x);
-      OUT_RING_F((box_y2 - dyo) * src_scale_y);
+      OUT_BATCH_F(box_x1 + pix_xoff);
+      OUT_BATCH_F(box_y2 + pix_yoff);
+      OUT_BATCH_F((box_x1 - dxo) * src_scale_x);
+      OUT_BATCH_F((box_y2 - dyo) * src_scale_y);
 
       /* top left */
-      OUT_RING_F(box_x1 + pix_xoff);
-      OUT_RING_F(box_y1 + pix_yoff);
-      OUT_RING_F((box_x1 - dxo) * src_scale_x);
-      OUT_RING_F((box_y1 - dyo) * src_scale_y);
+      OUT_BATCH_F(box_x1 + pix_xoff);
+      OUT_BATCH_F(box_y1 + pix_yoff);
+      OUT_BATCH_F((box_x1 - dxo) * src_scale_x);
+      OUT_BATCH_F((box_y1 - dyo) * src_scale_y);
 
-      ADVANCE_LP_RING();
+      ADVANCE_BATCH();
    }
 
    i830MarkSync(pScrn);
diff --git a/src/i965_render.c b/src/i965_render.c
index 172a1dc1..7f798e6c 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -924,72 +924,72 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
      * rendering pipe
      */
     {
-	BEGIN_LP_RING(2);
-   	OUT_RING(MI_FLUSH |
-		 MI_STATE_INSTRUCTION_CACHE_FLUSH |
-		 BRW_MI_GLOBAL_SNAPSHOT_RESET);
-	OUT_RING(MI_NOOP);
-	ADVANCE_LP_RING();
+	BEGIN_BATCH(2);
+	OUT_BATCH(MI_FLUSH |
+		  MI_STATE_INSTRUCTION_CACHE_FLUSH |
+		  BRW_MI_GLOBAL_SNAPSHOT_RESET);
+	OUT_BATCH(MI_NOOP);
+	ADVANCE_BATCH();
     }
     {
-        BEGIN_LP_RING(12);
+        BEGIN_BATCH(12);
 
         /* Match Mesa driver setup */
 	if (IS_IGD_GM(pI830))
-	    OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+	    OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 	else
-	    OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+	    OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 
-   	OUT_RING(BRW_CS_URB_STATE | 0);
-   	OUT_RING((0 << 4) |  /* URB Entry Allocation Size */
-		 (0 << 0));  /* Number of URB Entries */
+	OUT_BATCH(BRW_CS_URB_STATE | 0);
+	OUT_BATCH((0 << 4) |  /* URB Entry Allocation Size */
+		  (0 << 0));  /* Number of URB Entries */
 
 	/* Zero out the two base address registers so all offsets are
 	 * absolute.
 	 */
-   	OUT_RING(BRW_STATE_BASE_ADDRESS | 4);
-   	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* Generate state base address */
-   	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* Surface state base address */
-   	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* media base addr, don't care */
+	OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* Generate state base address */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* Surface state base address */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* media base addr, don't care */
 	/* general state max addr, disabled */
-   	OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
 	/* media object state max addr, disabled */
-   	OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
 
 	/* Set system instruction pointer */
-   	OUT_RING(BRW_STATE_SIP | 0);
-   	OUT_RING(state_base_offset + sip_kernel_offset);
-	OUT_RING(MI_NOOP);
-	ADVANCE_LP_RING();
+	OUT_BATCH(BRW_STATE_SIP | 0);
+	OUT_BATCH(state_base_offset + sip_kernel_offset);
+	OUT_BATCH(MI_NOOP);
+	ADVANCE_BATCH();
     }
     {
-	BEGIN_LP_RING(26);
+	BEGIN_BATCH(26);
 	/* Pipe control */
-   	OUT_RING(BRW_PIPE_CONTROL |
-		 BRW_PIPE_CONTROL_NOWRITE |
-		 BRW_PIPE_CONTROL_IS_FLUSH |
-		 2);
-   	OUT_RING(0);			       /* Destination address */
-   	OUT_RING(0);			       /* Immediate data low DW */
-   	OUT_RING(0);			       /* Immediate data high DW */
+	OUT_BATCH(BRW_PIPE_CONTROL |
+		  BRW_PIPE_CONTROL_NOWRITE |
+		  BRW_PIPE_CONTROL_IS_FLUSH |
+		  2);
+	OUT_BATCH(0);			       /* Destination address */
+	OUT_BATCH(0);			       /* Immediate data low DW */
+	OUT_BATCH(0);			       /* Immediate data high DW */
 
 	/* Binding table pointers */
-   	OUT_RING(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
-   	OUT_RING(0); /* vs */
-   	OUT_RING(0); /* gs */
-   	OUT_RING(0); /* clip */
-   	OUT_RING(0); /* sf */
+	OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
+	OUT_BATCH(0); /* vs */
+	OUT_BATCH(0); /* gs */
+	OUT_BATCH(0); /* clip */
+	OUT_BATCH(0); /* sf */
 	/* Only the PS uses the binding table */
-   	OUT_RING(state_base_offset + binding_table_offset); /* ps */
+	OUT_BATCH(state_base_offset + binding_table_offset); /* ps */
 
 	/* The drawing rectangle clipping is always on.  Set it to values that
 	 * shouldn't do any clipping.
 	 */
-   	OUT_RING(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
-   	OUT_RING(0x00000000);	/* ymin, xmin */
-	OUT_RING(DRAW_YMAX(pDst->drawable.height - 1) |
-		 DRAW_XMAX(pDst->drawable.width - 1)); /* ymax, xmax */
-   	OUT_RING(0x00000000);	/* yorigin, xorigin */
+	OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
+	OUT_BATCH(0x00000000);	/* ymin, xmin */
+	OUT_BATCH(DRAW_YMAX(pDst->drawable.height - 1) |
+		  DRAW_XMAX(pDst->drawable.width - 1)); /* ymax, xmax */
+	OUT_BATCH(0x00000000);	/* yorigin, xorigin */
 
 	/* skip the depth buffer */
 	/* skip the polygon stipple */
@@ -997,83 +997,83 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
 	/* skip the line stipple */
 
 	/* Set the pointers to the 3d pipeline state */
-   	OUT_RING(BRW_3DSTATE_PIPELINED_POINTERS | 5);
-   	OUT_RING(state_base_offset + vs_offset);  /* 32 byte aligned */
-   	OUT_RING(BRW_GS_DISABLE);   /* disable GS, resulting in passthrough */
-   	OUT_RING(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
-   	OUT_RING(state_base_offset + sf_offset);  /* 32 byte aligned */
-   	OUT_RING(state_base_offset + wm_offset);  /* 32 byte aligned */
-   	OUT_RING(state_base_offset + cc_offset);  /* 64 byte aligned */
+	OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
+	OUT_BATCH(state_base_offset + vs_offset);  /* 32 byte aligned */
+	OUT_BATCH(BRW_GS_DISABLE);   /* disable GS, resulting in passthrough */
+	OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
+	OUT_BATCH(state_base_offset + sf_offset);  /* 32 byte aligned */
+	OUT_BATCH(state_base_offset + wm_offset);  /* 32 byte aligned */
+	OUT_BATCH(state_base_offset + cc_offset);  /* 64 byte aligned */
 
 	/* URB fence */
-   	OUT_RING(BRW_URB_FENCE |
-        	 UF0_CS_REALLOC |
-	    	 UF0_SF_REALLOC |
-	    	 UF0_CLIP_REALLOC |
-	         UF0_GS_REALLOC |
-	         UF0_VS_REALLOC |
-	    	 1);
-   	OUT_RING(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
-	    	 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
-	    	 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
-   	OUT_RING(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
-	     	 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
+	OUT_BATCH(BRW_URB_FENCE |
+		  UF0_CS_REALLOC |
+		  UF0_SF_REALLOC |
+		  UF0_CLIP_REALLOC |
+		  UF0_GS_REALLOC |
+		  UF0_VS_REALLOC |
+		  1);
+	OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
+		  ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
+		  ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
+	OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
+		  ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
 
 	/* Constant buffer state */
-   	OUT_RING(BRW_CS_URB_STATE | 0);
-   	OUT_RING(((URB_CS_ENTRY_SIZE - 1) << 4) |
-	    	 (URB_CS_ENTRIES << 0));
-	ADVANCE_LP_RING();
+	OUT_BATCH(BRW_CS_URB_STATE | 0);
+	OUT_BATCH(((URB_CS_ENTRY_SIZE - 1) << 4) |
+		  (URB_CS_ENTRIES << 0));
+	ADVANCE_BATCH();
     }
     {
         int nelem = pMask ? 3: 2;
-   	BEGIN_LP_RING(pMask?12:10);
+	BEGIN_BATCH(pMask?12:10);
 	/* Set up the pointer to our vertex buffer */
-   	OUT_RING(BRW_3DSTATE_VERTEX_BUFFERS | 3);
-   	OUT_RING((0 << VB0_BUFFER_INDEX_SHIFT) |
-	    	 VB0_VERTEXDATA |
-	    	 ((4 * 2 * nelem) << VB0_BUFFER_PITCH_SHIFT));
-   	OUT_RING(state_base_offset + vb_offset);
-        OUT_RING(3);
-   	OUT_RING(0); // ignore for VERTEXDATA, but still there
+	OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3);
+	OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
+		  VB0_VERTEXDATA |
+		  ((4 * 2 * nelem) << VB0_BUFFER_PITCH_SHIFT));
+	OUT_BATCH(state_base_offset + vb_offset);
+        OUT_BATCH(3);
+	OUT_BATCH(0); // ignore for VERTEXDATA, but still there
 
 	/* Set up our vertex elements, sourced from the single vertex buffer.
 	 */
-   	OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * nelem) - 1));
+	OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * nelem) - 1));
 	/* vertex coordinates */
-   	OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
-	    	 VE0_VALID |
-	    	 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
-	    	 (0 << VE0_OFFSET_SHIFT));
-   	OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-	    	 (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
-	     	 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
-	    	 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
-	    	 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+	OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+		  VE0_VALID |
+		  (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+		  (0 << VE0_OFFSET_SHIFT));
+	OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+		  (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+		  (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+		  (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+		  (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
 	/* u0, v0 */
-   	OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
-	    	 VE0_VALID |
-	    	 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
-	    	 (8 << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
-   	OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-	    	 (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
-	    	 (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
-	    	 (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
-	    	 (8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
+	OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+		  VE0_VALID |
+		  (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+		  (8 << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
+	OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+		  (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+		  (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
+		  (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
+		  (8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
 	/* u1, v1 */
    	if (pMask) {
-	    OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
-		     VE0_VALID |
-		     (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
-		     (16 << VE0_OFFSET_SHIFT));
-	    OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-		     (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
-		     (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
-		     (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
-		     (10 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+	    OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+		      VE0_VALID |
+		      (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+		      (16 << VE0_OFFSET_SHIFT));
+	    OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+		      (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+		      (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
+		      (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
+		      (10 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
    	}
 
-   	ADVANCE_LP_RING();
+	ADVANCE_BATCH();
     }
 
 #ifdef I830DEBUG
@@ -1155,18 +1155,18 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
     }
 
     {
-      BEGIN_LP_RING(6);
-      OUT_RING(BRW_3DPRIMITIVE |
-	       BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL |
-	       (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) |
-	       (0 << 9) |  /* CTG - indirect vertex count */
-	       4);
-      OUT_RING(3);  /* vertex count per instance */
-      OUT_RING(0); /* start vertex offset */
-      OUT_RING(1); /* single instance */
-      OUT_RING(0); /* start instance location */
-      OUT_RING(0); /* index buffer offset, ignored */
-      ADVANCE_LP_RING();
+      BEGIN_BATCH(6);
+      OUT_BATCH(BRW_3DPRIMITIVE |
+		BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL |
+		(_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) |
+		(0 << 9) |  /* CTG - indirect vertex count */
+		4);
+      OUT_BATCH(3);  /* vertex count per instance */
+      OUT_BATCH(0); /* start vertex offset */
+      OUT_BATCH(1); /* single instance */
+      OUT_BATCH(0); /* start instance location */
+      OUT_BATCH(0); /* index buffer offset, ignored */
+      ADVANCE_BATCH();
     }
 #ifdef I830DEBUG
     ErrorF("sync after 3dprimitive");
@@ -1175,17 +1175,17 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
     /* we must be sure that the pipeline is flushed before next exa draw,
        because that will be new state, binding state and instructions*/
     {
-	BEGIN_LP_RING(4);
-   	OUT_RING(BRW_PIPE_CONTROL |
-	    BRW_PIPE_CONTROL_NOWRITE |
-	    BRW_PIPE_CONTROL_WC_FLUSH |
-	    BRW_PIPE_CONTROL_IS_FLUSH |
-	    (1 << 10) |  /* XXX texture cache flush for BLC/CTG */
-	    2);
-   	OUT_RING(0); /* Destination address */
-   	OUT_RING(0); /* Immediate data low DW */
-   	OUT_RING(0); /* Immediate data high DW */
-	ADVANCE_LP_RING();
+	BEGIN_BATCH(4);
+	OUT_BATCH(BRW_PIPE_CONTROL |
+		  BRW_PIPE_CONTROL_NOWRITE |
+		  BRW_PIPE_CONTROL_WC_FLUSH |
+		  BRW_PIPE_CONTROL_IS_FLUSH |
+		  (1 << 10) |  /* XXX texture cache flush for BLC/CTG */
+		  2);
+	OUT_BATCH(0); /* Destination address */
+	OUT_BATCH(0); /* Immediate data low DW */
+	OUT_BATCH(0); /* Immediate data high DW */
+	ADVANCE_BATCH();
     }
 
     /* Mark sync so we can wait for it before setting up the VB on the next
diff --git a/src/i965_video.c b/src/i965_video.c
index f84c6647..41f56a9d 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -497,89 +497,89 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
     wm_state->wm5.early_depth_test = 1;
 
     {
-	BEGIN_LP_RING(2);
-	OUT_RING(MI_FLUSH |
-		 MI_STATE_INSTRUCTION_CACHE_FLUSH |
-		 BRW_MI_GLOBAL_SNAPSHOT_RESET);
-	OUT_RING(MI_NOOP);
-	ADVANCE_LP_RING();
+	BEGIN_BATCH(2);
+	OUT_BATCH(MI_FLUSH |
+		  MI_STATE_INSTRUCTION_CACHE_FLUSH |
+		  BRW_MI_GLOBAL_SNAPSHOT_RESET);
+	OUT_BATCH(MI_NOOP);
+	ADVANCE_BATCH();
     }
 
     /* brw_debug (pScrn, "before base address modify"); */
     {
-	BEGIN_LP_RING(12);
+	BEGIN_BATCH(12);
 	/* Match Mesa driver setup */
 	if (IS_IGD_GM(pI830))
-	    OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+	    OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 	else
-	    OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+	    OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 
 	/* Mesa does this. Who knows... */
-	OUT_RING(BRW_CS_URB_STATE | 0);
-	OUT_RING((0 << 4) |	/* URB Entry Allocation Size */
-		 (0 << 0));	/* Number of URB Entries */
+	OUT_BATCH(BRW_CS_URB_STATE | 0);
+	OUT_BATCH((0 << 4) |	/* URB Entry Allocation Size */
+		  (0 << 0));	/* Number of URB Entries */
 
 	/* Zero out the two base address registers so all offsets are
 	 * absolute
 	 */
-	OUT_RING(BRW_STATE_BASE_ADDRESS | 4);
-	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* Generate state base address */
-	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* Surface state base address */
-	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* media base addr, don't care */
+	OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* Generate state base address */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* Surface state base address */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* media base addr, don't care */
 	/* general state max addr, disabled */
-	OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
 	/* media object state max addr, disabled */
-	OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
 
 	/* Set system instruction pointer */
-	OUT_RING(BRW_STATE_SIP | 0);
+	OUT_BATCH(BRW_STATE_SIP | 0);
 	/* system instruction pointer */
-	OUT_RING(state_base_offset + sip_kernel_offset);
+	OUT_BATCH(state_base_offset + sip_kernel_offset);
 
-	OUT_RING(MI_NOOP);
-	ADVANCE_LP_RING();
+	OUT_BATCH(MI_NOOP);
+	ADVANCE_BATCH();
     }
 
     /* brw_debug (pScrn, "after base address modify"); */
 
     {
-       BEGIN_LP_RING(42);
+       BEGIN_BATCH(42);
        /* Enable VF statistics */
-       OUT_RING(BRW_3DSTATE_VF_STATISTICS | 1);
+       OUT_BATCH(BRW_3DSTATE_VF_STATISTICS | 1);
 
        /* Pipe control */
-       OUT_RING(BRW_PIPE_CONTROL |
-		BRW_PIPE_CONTROL_NOWRITE |
-		BRW_PIPE_CONTROL_IS_FLUSH |
-		2);
-       OUT_RING(0);			/* Destination address */
-       OUT_RING(0);			/* Immediate data low DW */
-       OUT_RING(0);			/* Immediate data high DW */
+       OUT_BATCH(BRW_PIPE_CONTROL |
+		 BRW_PIPE_CONTROL_NOWRITE |
+		 BRW_PIPE_CONTROL_IS_FLUSH |
+		 2);
+       OUT_BATCH(0);			/* Destination address */
+       OUT_BATCH(0);			/* Immediate data low DW */
+       OUT_BATCH(0);			/* Immediate data high DW */
 
        /* Binding table pointers */
-       OUT_RING(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
-       OUT_RING(0); /* vs */
-       OUT_RING(0); /* gs */
-       OUT_RING(0); /* clip */
-       OUT_RING(0); /* sf */
+       OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
+       OUT_BATCH(0); /* vs */
+       OUT_BATCH(0); /* gs */
+       OUT_BATCH(0); /* clip */
+       OUT_BATCH(0); /* sf */
        /* Only the PS uses the binding table */
-       OUT_RING(state_base_offset + binding_table_offset); /* ps */
+       OUT_BATCH(state_base_offset + binding_table_offset); /* ps */
 
        /* Blend constant color (magenta is fun) */
-       OUT_RING(BRW_3DSTATE_CONSTANT_COLOR | 3);
-       OUT_RING(float_to_uint (1.0));
-       OUT_RING(float_to_uint (0.0));
-       OUT_RING(float_to_uint (1.0));
-       OUT_RING(float_to_uint (1.0));
+       OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3);
+       OUT_BATCH(float_to_uint (1.0));
+       OUT_BATCH(float_to_uint (0.0));
+       OUT_BATCH(float_to_uint (1.0));
+       OUT_BATCH(float_to_uint (1.0));
 
        /* The drawing rectangle clipping is always on.  Set it to values that
 	* shouldn't do any clipping.
 	*/
-       OUT_RING(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
-       OUT_RING(0x00000000);			/* ymin, xmin */
-       OUT_RING((pScrn->virtualX - 1) |
-		(pScrn->virtualY - 1) << 16);	/* ymax, xmax */
-       OUT_RING(0x00000000);			/* yorigin, xorigin */
+       OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
+       OUT_BATCH(0x00000000);			/* ymin, xmin */
+       OUT_BATCH((pScrn->virtualX - 1) |
+		 (pScrn->virtualY - 1) << 16);	/* ymax, xmax */
+       OUT_BATCH(0x00000000);			/* yorigin, xorigin */
 
        /* skip the depth buffer */
        /* skip the polygon stipple */
@@ -587,69 +587,69 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
        /* skip the line stipple */
 
        /* Set the pointers to the 3d pipeline state */
-       OUT_RING(BRW_3DSTATE_PIPELINED_POINTERS | 5);
-       OUT_RING(state_base_offset + vs_offset);  /* 32 byte aligned */
+       OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
+       OUT_BATCH(state_base_offset + vs_offset);  /* 32 byte aligned */
        /* disable GS, resulting in passthrough */
-       OUT_RING(BRW_GS_DISABLE);
+       OUT_BATCH(BRW_GS_DISABLE);
        /* disable CLIP, resulting in passthrough */
-       OUT_RING(BRW_CLIP_DISABLE);
-       OUT_RING(state_base_offset + sf_offset);  /* 32 byte aligned */
-       OUT_RING(state_base_offset + wm_offset);  /* 32 byte aligned */
-       OUT_RING(state_base_offset + cc_offset);  /* 64 byte aligned */
+       OUT_BATCH(BRW_CLIP_DISABLE);
+       OUT_BATCH(state_base_offset + sf_offset);  /* 32 byte aligned */
+       OUT_BATCH(state_base_offset + wm_offset);  /* 32 byte aligned */
+       OUT_BATCH(state_base_offset + cc_offset);  /* 64 byte aligned */
 
        /* URB fence */
-       OUT_RING(BRW_URB_FENCE |
-		UF0_CS_REALLOC |
-		UF0_SF_REALLOC |
-		UF0_CLIP_REALLOC |
-		UF0_GS_REALLOC |
-		UF0_VS_REALLOC |
-		1);
-       OUT_RING(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
-		((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
-		((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
-       OUT_RING(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
-		((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
+       OUT_BATCH(BRW_URB_FENCE |
+		 UF0_CS_REALLOC |
+		 UF0_SF_REALLOC |
+		 UF0_CLIP_REALLOC |
+		 UF0_GS_REALLOC |
+		 UF0_VS_REALLOC |
+		 1);
+       OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
+		 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
+		 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
+       OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
+		 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
 
        /* Constant buffer state */
-       OUT_RING(BRW_CS_URB_STATE | 0);
-       OUT_RING(((URB_CS_ENTRY_SIZE - 1) << 4) |
-		(URB_CS_ENTRIES << 0));
+       OUT_BATCH(BRW_CS_URB_STATE | 0);
+       OUT_BATCH(((URB_CS_ENTRY_SIZE - 1) << 4) |
+		 (URB_CS_ENTRIES << 0));
 
        /* Set up the pointer to our vertex buffer */
-       OUT_RING(BRW_3DSTATE_VERTEX_BUFFERS | 2);
+       OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 2);
        /* four 32-bit floats per vertex */
-       OUT_RING((0 << VB0_BUFFER_INDEX_SHIFT) |
-		VB0_VERTEXDATA |
-		((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
-       OUT_RING(state_base_offset + vb_offset);
-       OUT_RING(3); /* four corners to our rectangle */
+       OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
+		 VB0_VERTEXDATA |
+		 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
+       OUT_BATCH(state_base_offset + vb_offset);
+       OUT_BATCH(3); /* four corners to our rectangle */
 
        /* Set up our vertex elements, sourced from the single vertex buffer. */
-       OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
+       OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
        /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
-       OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
-		VE0_VALID |
-		(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
-		(0 << VE0_OFFSET_SHIFT));
-       OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-		(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
-		(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
-		(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
-		(0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+       OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+		 VE0_VALID |
+		 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+		 (0 << VE0_OFFSET_SHIFT));
+       OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+		 (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+		 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
        /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
-       OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
-		VE0_VALID |
-		(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
-		(8 << VE0_OFFSET_SHIFT));
-       OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-		(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
-		(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
-		(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
-		(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
-
-       OUT_RING(MI_NOOP);			/* pad to quadword */
-       ADVANCE_LP_RING();
+       OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+		 VE0_VALID |
+		 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+		 (8 << VE0_OFFSET_SHIFT));
+       OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+		 (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+		 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+
+       OUT_BATCH(MI_NOOP);			/* pad to quadword */
+       ADVANCE_BATCH();
     }
 
    /* Set up the offset for translating from the given region (in screen
@@ -750,18 +750,18 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
 	       BRW_TS_CTL_SNAPSHOT_ENABLE);
 #endif
 
-	BEGIN_LP_RING(6);
-	OUT_RING(BRW_3DPRIMITIVE |
-		 BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL |
-		 (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) |
-		 (0 << 9) |  /* CTG - indirect vertex count */
-		 4);
-	OUT_RING(3); /* vertex count per instance */
-	OUT_RING(0); /* start vertex offset */
-	OUT_RING(1); /* single instance */
-	OUT_RING(0); /* start instance location */
-	OUT_RING(0); /* index buffer offset, ignored */
-	ADVANCE_LP_RING();
+	BEGIN_BATCH(6);
+	OUT_BATCH(BRW_3DPRIMITIVE |
+		  BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL |
+		  (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) |
+		  (0 << 9) |  /* CTG - indirect vertex count */
+		  4);
+	OUT_BATCH(3); /* vertex count per instance */
+	OUT_BATCH(0); /* start vertex offset */
+	OUT_BATCH(1); /* single instance */
+	OUT_BATCH(0); /* start instance location */
+	OUT_BATCH(0); /* index buffer offset, ignored */
+	ADVANCE_BATCH();
 
 #if 0
 	for (j = 0; j < 100000; j++) {
author	Jesse Barnes <jbarnes@nietzche.virtuousgeek.org>	2008-03-17 15:19:05 -0700
committer	Jesse Barnes <jbarnes@nietzche.virtuousgeek.org>	2008-03-17 15:19:05 -0700
commit	ffb5a115cc62ed63110f77815b7f04976f720065 (patch)
tree	bebc956a00ed8a302e3df575eb0ee0249cc12ca9
parent	05cf07071e25f84dec3476a9bed7235ed50cd249 (diff)
parent	24e6eb2ae683ed6614ac79c0d7811ac9fe94209f (diff)