diff options
| author | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-01-09 21:27:42 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-01-09 21:27:42 +0800 |
| commit | 2f0c0427dc4113bac64cda07c6365df1f0637697 (patch) | |
| tree | 429649e41e436b2719936149de9138a084adb5df /src/brw_structs.h | |
| parent | 139e9affdd49dcbe08e260a0a2bd001de16566e6 (diff) | |
Update PIPELINE_SELECT instruction and surface state format for new chipset
Diffstat (limited to 'src/brw_structs.h')
| -rw-r--r-- | src/brw_structs.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/brw_structs.h b/src/brw_structs.h index 28d8e127..d4fc5c67 100644 --- a/src/brw_structs.h +++ b/src/brw_structs.h @@ -832,9 +832,8 @@ struct brw_wm_unit_state unsigned int program_computes_depth:1; unsigned int program_uses_killpixel:1; unsigned int legacy_line_rast: 1; - unsigned int pad1:1; - unsigned int max_threads:6; - unsigned int pad2:1; + unsigned int transposed_urb_read:1; + unsigned int max_threads:7; } wm5; float global_depth_offset_constant; @@ -977,6 +976,13 @@ struct brw_surface_state unsigned int min_array_elt:9; unsigned int min_lod:4; } ss4; + + struct { + unsigned int pad:20; + unsigned int y_offset:4; + unsigned int pad2:1; + unsigned int x_offset:7; + } ss5; }; |