diff options
| author | Keith Packard <keithp@keithp.com> | 2008-03-31 23:50:20 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2008-03-31 23:50:20 -0700 |
| commit | a6492661ae07310128eb73c3ef037c42ce7ab184 (patch) | |
| tree | 0d72faeb2195da4618bf0d1f8fce460e80c99a74 /src/exa_wm_write.g4a | |
| parent | f8081178eb6fda0e405967cbacad532561619262 (diff) | |
Fix composite with mask using new compositing thread code
Clean up register allocation to never overlap
Always write 4 values for each texture vertex.
Diffstat (limited to 'src/exa_wm_write.g4a')
| -rw-r--r-- | src/exa_wm_write.g4a | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/exa_wm_write.g4a b/src/exa_wm_write.g4a index 9a821d72..5d3e6b1e 100644 --- a/src/exa_wm_write.g4a +++ b/src/exa_wm_write.g4a @@ -31,9 +31,6 @@ include(`exa_wm.g4i') -/* m0, m1 are all direct passed by PS thread payload */ -mov (8) m1<1>F g1<8,8,1>F { align1 }; - /* prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2), then it's ready to write */ /* src_sample0 -> m2 src_sample1 -> m6 @@ -55,7 +52,7 @@ mov (8) m8<1>F src_sample5<8,8,1>F { align1 }; mov (8) m9<1>F src_sample7<8,8,1>F { align1 }; /* m0, m1 are all direct passed by PS thread payload */ -mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable }; +mov (8) m1<1>UD g1<8,8,1>UD { align1 }; /* write */ send (16) 0 acc0<1>UW g0<8,8,1>UW write ( @@ -76,5 +73,4 @@ nop; nop; nop; nop; -nop; |