uxa: Limit maximum size of tiled objects

On older chipsets (i.e. pre-i965) tiling is very restrictive and imposes
severe size and alignment constraints. Combine that with relatively
small apertures and it is very easy to create a batch buffer that
cannot be mapped into the aperture (but would otherwise fit based purely
on total object size). To prevent this we need to not use tiling for large
buffers (the very same buffers where tiling would be of most benefit!).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/i830.h b/src/i830.h
index 91ea1c15..c8950217 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -311,6 +311,7 @@ typedef struct intel_screen_private {
 	int accel_max_x;
 	int accel_max_y;
 	int max_gtt_map_size;
+	int max_tiling_size;
 
 	Bool XvDisabled;	/* Xv disabled in PreInit. */
 	Bool XvEnabled;		/* Xv enabled for this generation. */
@@ -467,6 +468,7 @@ unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long siz
 unsigned long i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
 				   uint32_t tiling_mode);
 void i830_set_max_gtt_map_size(ScrnInfoPtr scrn);
+void i830_set_max_tiling_size(ScrnInfoPtr scrn);
 
 i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn);