Replace I830Sync's irq emit/wait code with bufmgr use.

This pre-GEM code was all sorts of broken -- see intel_bufmgr_fake.c for
the hoops that must be jumped to use that kernel interface successfully.
Yet we continued to use it even with KMS/DRI2/UXA, which may account for
some hangs.

1 files changed, 27 insertions, 2 deletions

diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c
index ff5f0c21..5a9f9c5c 100644
--- a/src/i830_batchbuffer.c
+++ b/src/i830_batchbuffer.c
@@ -159,8 +159,13 @@ intel_batch_teardown(ScrnInfoPtr pScrn)
 
     if (pI830->batch_ptr != NULL) {
 	dri_bo_unmap(pI830->batch_bo);
-	dri_bo_unreference(pI830->batch_bo);
 	pI830->batch_ptr = NULL;
+
+	dri_bo_unreference(pI830->batch_bo);
+	pI830->batch_bo = NULL;
+
+	dri_bo_unreference(pI830->last_batch_bo);
+	pI830->last_batch_bo = NULL;
     }
 }
 
@@ -201,7 +206,13 @@ intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
     if (ret != 0)
 	FatalError("Failed to submit batchbuffer: %s\n", strerror(-ret));
 
-    dri_bo_unreference(pI830->batch_bo);
+    /* Save a ref to the last batch emitted, which we use for syncing
+     * in debug code.
+     */
+    dri_bo_unreference(pI830->last_batch_bo);
+    pI830->last_batch_bo = pI830->batch_bo;
+    pI830->batch_bo = NULL;
+
     intel_next_batch(pScrn);
 
     /* Mark that we need to flush whatever potential rendering we've done in the
@@ -214,3 +225,17 @@ intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
     if (pI830->batch_flush_notify)
 	pI830->batch_flush_notify (pScrn);
 }
+
+/** Waits on the last emitted batchbuffer to be completed. */
+void
+intel_batch_wait_last(ScrnInfoPtr scrn)
+{
+    I830Ptr pI830 = I830PTR(scrn);
+
+    /* Map it CPU write, which guarantees it's done.  This is a completely
+     * non performance path, so we don't need anything better.
+     */
+    drm_intel_bo_map(pI830->last_batch_bo, TRUE);
+    drm_intel_bo_unmap(pI830->last_batch_bo);
+}
+