diff options
| author | Eric Anholt <eric@anholt.net> | 2007-03-13 17:07:10 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2007-03-13 17:07:10 -0700 |
| commit | 66fdb08c83d353fbe4e917900c54b555c869eb80 (patch) | |
| tree | e7f4fec6ff189437d90a3f639373d80f590fcc84 /src/i830_debug.c | |
| parent | 44708bdd9ebfef0328302c9a964b80deb46e57c6 (diff) | |
Refine the i855 LVDS clock code. In particular, p2 is always 14.
This gets correct clocks detected on most harware. The SSC is always assumed
to be 66Mhz, which may not be true, but we'll fix that when we find example
hardware.
Diffstat (limited to 'src/i830_debug.c')
| -rw-r--r-- | src/i830_debug.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/i830_debug.c b/src/i830_debug.c index dccaa7ea..7fd94416 100644 --- a/src/i830_debug.c +++ b/src/i830_debug.c @@ -187,25 +187,24 @@ DEBUGSTRING(i830_debug_dpll) } else { Bool is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B); - if (val & PLL_P2_DIVIDE_BY_4) - p2 = 4; - else - p2 = 2; - if (is_lvds) { mode = "LVDS"; - /* Map the bit number set from (1, 6) to (-1, 4). */ p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT); + p2 = 14; } else { mode = "DAC/serial"; if (val & PLL_P1_DIVIDE_BY_TWO) { p1 = 2; } else { - /* Map the number in the field to (1, 31) */ + /* Map the number in the field to (3, 33) */ p1 = ((val & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; } + if (val & PLL_P2_DIVIDE_BY_4) + p2 = 4; + else + p2 = 2; } } |