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| author | Jesse Barnes <jesse.barnes@intel.com> | 2007-11-01 12:06:07 -0700 |
|---|---|---|
| committer | Jesse Barnes <jesse.barnes@intel.com> | 2007-11-01 12:06:07 -0700 |
| commit | b434c1a437c407de88396b219560649c2dae82b2 (patch) | |
| tree | 8c61c4e3056e1434684ce697b890049194b90b59 /src/i830_display.c | |
| parent | 50d3693a6862028e50bc5ba8c788e7ea573c3eb8 (diff) | |
Framebuffer compression fix: front buffer may not be at fence 0
Fix a long standing bug in the framebuffer compression code (thanks to
Pierre Willenbrock!) that prevented FBC from working correctly if the front
buffer was anywhere but fence register 0.
Diffstat (limited to 'src/i830_display.c')
| -rw-r--r-- | src/i830_display.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/i830_display.c b/src/i830_display.c index a99b4a55..d988b867 100644 --- a/src/i830_display.c +++ b/src/i830_display.c @@ -611,6 +611,7 @@ i830_enable_fb_compression(xf86CrtcPtr crtc) fbc_ctl |= (compressed_stride & 0xff) << FBC_CTL_STRIDE_SHIFT; fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; fbc_ctl |= FBC_CTL_UNCOMPRESSIBLE; + fbc_ctl |= pI830->front_buffer->fence_nr; OUTREG(FBC_CONTROL, fbc_ctl); xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc enabled on plane %c\n", plane ? |