Tiling fixes for 965

This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text.  This
is likely another tiling related problem with the composite hook.

1 files changed, 21 insertions, 1 deletions

diff --git a/src/i830_display.c b/src/i830_display.c
index 6fe7be74..d5f75867 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -498,6 +498,23 @@ i830_pipe_a_require_deactivate (ScrnInfoPtr scrn)
     return;
 }
 
+/* FIXME: use pixmap private instead if possible */
+static Bool
+i830_display_tiled(xf86CrtcPtr crtc)
+{
+    ScrnInfoPtr pScrn = crtc->scrn;
+    I830Ptr pI830 = I830PTR(pScrn);
+
+    if (!pI830->tiling)
+	return FALSE;
+
+    /* Rotated data is currently linear, allocated either via XAA or EXA */
+    if (crtc->rotatedData)
+	return FALSE;
+
+    return TRUE;
+}
+
 static Bool
 i830_use_fb_compression(xf86CrtcPtr crtc)
 {
@@ -510,6 +527,9 @@ i830_use_fb_compression(xf86CrtcPtr crtc)
     if (!pI830->fb_compression)
 	return FALSE;
 
+    if (!i830_display_tiled(crtc))
+	return FALSE;
+
     /* Pre-965 only supports plane A */
     if (!IS_I965GM(pI830) && plane != FBC_CTL_PLANEA)
 	return FALSE;
@@ -1078,7 +1098,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
     else
 	dspcntr |= DISPPLANE_SEL_PIPE_B;
 
-    if (pI830->tiling)
+    if (IS_I965G(pI830) && i830_display_tiled(crtc))
 	dspcntr |= DISPLAY_PLANE_TILED;
 
     pipeconf = INREG(pipeconf_reg);