SDVO: Fix TV support

As SDVO TV uses SDVO_TVClkIn from SDVO encoder for clock reference,
it needs to generate proper PLL for current input clock. This uses
fixed PLL table from vbios for this. And possible sdvo mulitiplier
has to be setup correctly. This makes TV output stable on my 945GCLF2
board with NTSC-M format.

1 files changed, 22 insertions, 3 deletions

diff --git a/src/i830_display.c b/src/i830_display.c
index 8ecb5e57..8a5cf246 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1304,6 +1304,26 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 		   (float)adjusted_mode->Clock / 1000);
     }
 
+    /* SDVO TV has fixed PLL values depends on its clock range,
+       this mirrors vbios setting. */
+    if (is_sdvo && is_tv) {
+	if (adjusted_mode->Clock >= 100000 &&
+		adjusted_mode->Clock < 140500) {
+	    clock.p1 = 2;
+	    clock.p2 = 10;
+	    clock.n = 3;
+	    clock.m1 = 16;
+	    clock.m2 = 8;
+	} else if (adjusted_mode->Clock >= 140500 &&
+		adjusted_mode->Clock <= 200000) {
+	    clock.p1 = 1;
+	    clock.p2 = 10;
+	    clock.n = 6;
+	    clock.m1 = 12;
+	    clock.m2 = 8;
+	}
+    }
+
     fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
 
     dpll = DPLL_VGA_MODE_DIS;
@@ -1315,10 +1335,9 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 	if (is_sdvo)
 	{
 	    dpll |= DPLL_DVO_HIGH_SPEED;
-	    if ((IS_I945G(pI830) || IS_I945GM(pI830) || IS_G33CLASS(pI830)) &&
-		!is_tv)
+	    if ((IS_I945G(pI830) || IS_I945GM(pI830) || IS_G33CLASS(pI830)))
 	    {
-		int sdvo_pixel_multiply = adjusted_mode->Clock / mode->Clock;
+		int sdvo_pixel_multiply = i830_sdvo_get_pixel_multiplier (adjusted_mode);
 		dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
 	    }
 	}