diff options
| author | Eric Anholt <eric@anholt.net> | 2006-12-13 00:26:27 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2006-12-13 12:04:33 -0800 |
| commit | e27372e85a007d8a7e31678dbdb62755c22918bf (patch) | |
| tree | 800bffd8fbaf3bbacfd8fa6a610a33be58f6844e /src/i830_display.c | |
| parent | df0a5a25aa72563a33731f8063602dd7faad8459 (diff) | |
Add some caution with PCI write posting and DPLL delays to i830_crtc_dpms.
While it doesn't specifically help/hurt my test case, we've seen enough
mysterious behavior that caution is probably warranted.
Diffstat (limited to 'src/i830_display.c')
| -rw-r--r-- | src/i830_display.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/i830_display.c b/src/i830_display.c index e4d8e9f3..c111145e 100644 --- a/src/i830_display.c +++ b/src/i830_display.c @@ -507,6 +507,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode) /* Enable the DPLL */ temp = INREG(dpll_reg); OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE); + (void)INREG(dpll_reg); /* write posting */ /* Wait for the clocks to stabilize. */ usleep(150); @@ -538,6 +539,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode) /* Flush the plane changes */ OUTREG(dspbase_reg, INREG(dspbase_reg)); + (void)INREG(dspbase_reg); /* write posting */ if (!IS_I9XX(pI830)) { /* Wait for vblank for the disable to take effect */ @@ -547,12 +549,17 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode) /* Next, disable display pipes */ temp = INREG(pipeconf_reg); OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE); + (void)INREG(pipeconf_reg); /* write posting */ /* Wait for vblank for the disable to take effect. */ i830WaitForVblank(pScrn); temp = INREG(dpll_reg); OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE); + (void)INREG(dpll_reg); /* write posting */ + + /* Wait for the clocks to turn off. */ + usleep(150); break; } } |