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authorJesse Barnes <jbarnes@virtuousgeek.org>2009-01-26 17:14:06 -0800
committerEric Anholt <eric@anholt.net>2009-01-27 14:33:43 -0800
commit8d4bc36fae50b09a73ba2cfab920adb32141a358 (patch)
tree509111af04c4094f685431997d2749987dc30a8b /src/i830_dri.c
parent6c0ca1676bf60529dd331cc739abdf68fa9e918d (diff)
Support tiled back/depth on 915-class hardware with DRI2.
Set alignments, tile settings and flags correctly in the 2D driver to support tiled rendering. UXA's create pixmap function currently assumes the worst about the alignment constraints; that should probably be fixed. Some of the 1M alignment fixes could probably be done more cleanly as well.
Diffstat (limited to 'src/i830_dri.c')
-rw-r--r--src/i830_dri.c13
1 files changed, 4 insertions, 9 deletions
diff --git a/src/i830_dri.c b/src/i830_dri.c
index d6698daa..7a95d027 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -1570,7 +1570,7 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count)
pDraw->depth, 0);
switch (attachments[i]) {
case DRI2BufferDepth:
- if (IS_I965G(pI830))
+ if (SUPPORTS_YTILING(pI830))
tiling = I915_TILING_Y;
else
tiling = I915_TILING_X;
@@ -1583,19 +1583,14 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count)
break;
}
- /* Disable tiling on 915-class 3D for now. Because the 2D blitter
- * requires fence regs to operate, and they're not being managed
- * by the kernel yet, we don't want to expose tiled buffers to the
- * 3D client as it'll just render incorrectly if it pays attention
- * to our tiling bits at all.
- */
- if (!IS_I965G(pI830))
+ if (!pI830->tiling ||
+ (!IS_I965G(pI830) && !pI830->kernel_exec_fencing))
tiling = I915_TILING_NONE;
if (tiling != I915_TILING_NONE) {
bo = i830_get_pixmap_bo(pPixmap);
drm_intel_bo_set_tiling(bo, &tiling,
- pDraw->width * pDraw->bitsPerPixel / 8);
+ intel_get_pixmap_pitch(pPixmap));
}
}