diff options
| author | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-06-05 11:07:41 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2007-06-05 11:34:22 -0700 |
| commit | f4c05973d391bdb0a9b0eadb155548310baa98fd (patch) | |
| tree | 0e1f21768e1dfffdb0f06349780870c8df8ab563 /src/i830_dri.c | |
| parent | 36fcaeb2ef94db5399071540bba106dec3db81d5 (diff) | |
Add support for the G33, Q33, and Q35 chipsets.
These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
Diffstat (limited to 'src/i830_dri.c')
| -rw-r--r-- | src/i830_dri.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/i830_dri.c b/src/i830_dri.c index 663ef148..a17770bf 100644 --- a/src/i830_dri.c +++ b/src/i830_dri.c @@ -232,6 +232,22 @@ I830SetParam(ScrnInfoPtr pScrn, int param, int value) return TRUE; } +static Bool +I830SetHWS(ScrnInfoPtr pScrn, int addr) +{ + I830Ptr pI830 = I830PTR(pScrn); + drmI830HWS hws; + + hws.addr = addr; + + if (drmCommandWrite(pI830->drmSubFD, DRM_I830_HWS_PAGE_ADDR, + &hws, sizeof(drmI830HWS))) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "G33 status page initialization Failed\n"); + return FALSE; + } + return TRUE; +} static Bool I830InitVisualConfigs(ScreenPtr pScreen) @@ -933,6 +949,12 @@ I830DRIDoMappings(ScreenPtr pScreen) return FALSE; } + if (IS_G33CLASS(pI830)) { + if (!I830SetHWS(pScrn, pI830->hw_status->offset)) { + DRICloseScreen(pScreen); + return FALSE; + } + } /* init to zero to be safe */ sarea->front_handle = 0; sarea->back_handle = 0; |