diff options
| author | Eric Anholt <eric@anholt.net> | 2009-02-27 19:09:49 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-02-27 19:09:49 -0800 |
| commit | 5bfd73cd31ba197a62f549cdbad1a1270b571027 (patch) | |
| tree | 50430d9a372c5a69c84c73e8f7fdd7b48041f149 /src/i830_dri.c | |
| parent | f53bdad1412f841075232455837578f00709c6ef (diff) | |
Only allocate pixmaps aligned for tiling when requested by DRI2 GetBuffers.
This saves massive quantities of memory on pre-965 since the DRI2 tiling
enable caused the minimum size of any pixmap to be 1MB.
Diffstat (limited to 'src/i830_dri.c')
| -rw-r--r-- | src/i830_dri.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/src/i830_dri.c b/src/i830_dri.c index 540bf5e7..96c711e5 100644 --- a/src/i830_dri.c +++ b/src/i830_dri.c @@ -1561,36 +1561,33 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count) pPixmap = pDepthPixmap; pPixmap->refcnt++; } else { - uint32_t tiling = I915_TILING_NONE; + unsigned int hint = 0; - pPixmap = (*pScreen->CreatePixmap)(pScreen, - pDraw->width, - pDraw->height, - pDraw->depth, 0); switch (attachments[i]) { case DRI2BufferDepth: if (SUPPORTS_YTILING(pI830)) - tiling = I915_TILING_Y; + hint = INTEL_CREATE_PIXMAP_TILING_Y; else - tiling = I915_TILING_X; + hint = INTEL_CREATE_PIXMAP_TILING_X; break; case DRI2BufferFakeFrontLeft: case DRI2BufferFakeFrontRight: case DRI2BufferBackLeft: case DRI2BufferBackRight: - tiling = I915_TILING_X; + hint = INTEL_CREATE_PIXMAP_TILING_X; break; } if (!pI830->tiling || (!IS_I965G(pI830) && !pI830->kernel_exec_fencing)) - tiling = I915_TILING_NONE; + hint = 0; + + pPixmap = (*pScreen->CreatePixmap)(pScreen, + pDraw->width, + pDraw->height, + pDraw->depth, + hint); - if (tiling != I915_TILING_NONE) { - bo = i830_get_pixmap_bo(pPixmap); - drm_intel_bo_set_tiling(bo, &tiling, - intel_get_pixmap_pitch(pPixmap)); - } } if (attachments[i] == DRI2BufferDepth) |