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authorZhenyu Wang <zhenyuw@linux.intel.com>2009-06-08 10:22:14 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2009-06-10 10:26:03 +0800
commitfb524caa3e2f1f516717669642bb4b2244f9e7e4 (patch)
tree8b67edfe89deb7140123b429bd272c6d2fcf45f3 /src/i830_driver.c
parent4f40b33ef4b069b18a6a18406da83a23ca6e1127 (diff)
Remove fixed MMIO size
Use pci resource size instead, which will get the correct MMIO range. New chipset uses obviously larger MMIO range. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'src/i830_driver.c')
-rw-r--r--src/i830_driver.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 84008726..9d38fba1 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -425,7 +425,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
device = pI830->PciInfo;
err = pci_device_map_range (device,
pI830->MMIOAddr,
- I810_REG_SIZE,
+ pI830->MMIOSize,
PCI_DEV_MAP_FLAG_WRITABLE,
(void **) &pI830->MMIOBase);
if (err)
@@ -508,7 +508,7 @@ I830UnmapMMIO(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- pci_device_unmap_range (pI830->PciInfo, pI830->MMIOBase, I810_REG_SIZE);
+ pci_device_unmap_range (pI830->PciInfo, pI830->MMIOBase, pI830->MMIOSize);
pI830->MMIOBase = NULL;
if (IS_I9XX(pI830)) {
@@ -1218,6 +1218,7 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
if (pI830->pEnt->device->IOBase != 0) {
pI830->MMIOAddr = pI830->pEnt->device->IOBase;
from = X_CONFIG;
+ pI830->MMIOSize = I810_REG_SIZE;
} else {
pI830->MMIOAddr = I810_MEMBASE (pI830->PciInfo, mmio_bar);
if (pI830->MMIOAddr == 0) {
@@ -1226,10 +1227,11 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
PreInitCleanup(pScrn);
return FALSE;
}
+ pI830->MMIOSize = pI830->PciInfo->regions[mmio_bar].size;
}
- xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX\n",
- (unsigned long)pI830->MMIOAddr);
+ xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX size %u\n",
+ (unsigned long)pI830->MMIOAddr, pI830->MMIOSize);
/* Now figure out mapsize on 8xx chips */
if (IS_I830(pI830) || IS_845G(pI830)) {