diff options
| author | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-07-03 01:03:14 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-07-21 11:03:29 +0800 |
| commit | 483cba52ef62565fff3b21eb8ca2b00ab3075fa6 (patch) | |
| tree | e5b8cd740e76966a80f37ba9bde8a4a36f07f499 /src/i830_driver.c | |
| parent | cb4c1fa7499d82beb01566aaf1f323a03ebc1ae4 (diff) | |
Fix official name for GM45 chipset
(cherry picked from commit a34a4e3f6420e2b06bbdaa124fe0ccb1bc6a0bd9)
Diffstat (limited to 'src/i830_driver.c')
| -rw-r--r-- | src/i830_driver.c | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/src/i830_driver.c b/src/i830_driver.c index dff7d51f..0a49d3a2 100644 --- a/src/i830_driver.c +++ b/src/i830_driver.c @@ -251,7 +251,7 @@ static SymTabRec I830Chipsets[] = { {PCI_CHIP_G33_G, "G33"}, {PCI_CHIP_Q35_G, "Q35"}, {PCI_CHIP_Q33_G, "Q33"}, - {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"}, + {PCI_CHIP_GM45_GM, "Mobile Intel® GM45 Express Chipset"}, {PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"}, {PCI_CHIP_G45_G, "G45/G43"}, {PCI_CHIP_Q45_G, "Q45/Q43"}, @@ -278,7 +278,7 @@ static PciChipsets I830PciChipsets[] = { {PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA}, {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA}, {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA}, - {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA}, + {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, RES_SHARED_VGA}, {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA}, {PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA}, {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA}, @@ -653,7 +653,7 @@ I830MapMMIO(ScrnInfoPtr pScrn) if (IS_I965G(pI830)) { - if (IS_IGD_GM(pI830) || IS_G4X(pI830)) { + if (IS_GM45(pI830) || IS_G4X(pI830)) { gttaddr = pI830->MMIOAddr + MB(2); pI830->GTTMapSize = MB(2); } else { @@ -973,7 +973,7 @@ i830_init_clock_gating(ScrnInfoPtr pScrn) /* Disable clock gating reported to work incorrectly according to the specs. */ - if (IS_IGD_GM(pI830)) { + if (IS_GM45(pI830)) { OUTREG(RENCLK_GATE_D1, 0); OUTREG(RENCLK_GATE_D2, 0); OUTREG(RAMCLK_GATE_D, 0); @@ -1218,7 +1218,9 @@ i830_detect_chipset(ScrnInfoPtr pScrn) case PCI_CHIP_Q33_G: chipname = "Q33"; break; - case PCI_CHIP_IGD_GM: + case PCI_CHIP_GM45_GM: + chipname = "Mobile Intel® GM45 Express Chipset"; + break; case PCI_CHIP_IGD_E_G: chipname = "Intel Integrated Graphics Device"; break; @@ -1985,7 +1987,7 @@ i830_set_dsparb(ScrnInfoPtr pScrn) * FIFO RAM entries equally between planes A and B. */ if (IS_I9XX(pI830)) { - if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) + if (IS_I965GM(pI830) || IS_GM45(pI830)) OUTREG(DSPARB, (127 << DSPARB_CSTART_SHIFT) | (64 << DSPARB_BSTART_SHIFT)); else @@ -2143,7 +2145,7 @@ SaveHWState(ScrnInfoPtr pScrn) pI830->saveRAMCLK_GATE_D = INREG(RAMCLK_GATE_D); } - if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) + if (IS_I965GM(pI830) || IS_GM45(pI830)) pI830->savePWRCTXA = INREG(PWRCTXA); if (IS_MOBILE(pI830) && !IS_I830(pI830)) @@ -2213,7 +2215,7 @@ RestoreHWState(ScrnInfoPtr pScrn) OUTREG(RAMCLK_GATE_D, pI830->saveRAMCLK_GATE_D); } - if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) + if (IS_I965GM(pI830) || IS_GM45(pI830)) OUTREG(PWRCTXA, pI830->savePWRCTXA); /* @@ -2623,7 +2625,7 @@ i830_try_memory_allocation(ScrnInfoPtr pScrn) if (!i830_allocate_2d_memory(pScrn)) goto failed; - if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) + if (IS_I965GM(pI830) || IS_GM45(pI830)) if (!i830_allocate_pwrctx(pScrn)) goto failed; @@ -3036,7 +3038,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) * alone in that case. * Also make sure the DRM can handle the swap. */ - if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_IGD_GM(pI830) && + if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_GM45(pI830) && (!pI830->directRenderingEnabled || (pI830->directRenderingEnabled && pI830->drmMinor >= 10))) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "adjusting plane->pipe mappings " |