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authorKeith Packard <keithp@bouzouki.jf.intel.com>2006-12-14 16:51:48 -0800
committerKeith Packard <keithp@bouzouki.jf.intel.com>2006-12-14 16:51:48 -0800
commit082519f34b468d0c5aa08db74ff2b51cf411d743 (patch)
treeb077b64434d519ff085e514444cb520c2d371a29 /src/i830_driver.c
parent55e7a32096a58f7bb2380b04df6b3dd9dc8e5b6a (diff)
Turn pll/pipe/plane on in crtc_set_mode
Instead of delaying pll/pipe/plane enables to the dpms function, turn them on right away in the crtc_set_mode function. To avoid rewriting these registers in the subsequent dpms function, check each register written there to see if the enable bit is already on and don't rewrite.
Diffstat (limited to 'src/i830_driver.c')
-rw-r--r--src/i830_driver.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/src/i830_driver.c b/src/i830_driver.c
index a210b630..97f52853 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2225,15 +2225,25 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(FPA0, pI830->saveFPA0);
OUTREG(FPA1, pI830->saveFPA1);
- OUTREG(DPLL_A, pI830->saveDPLL_A);
if (IS_I965G(pI830))
OUTREG(DPLL_A_MD, pI830->saveDPLL_A_MD);
+ if (pI830->saveDPLL_A & DPLL_VCO_ENABLE)
+ {
+ OUTREG(DPLL_A, pI830->saveDPLL_A & ~DPLL_VCO_ENABLE);
+ usleep(150);
+ }
+ OUTREG(DPLL_A, pI830->saveDPLL_A);
if(xf86_config->num_crtc == 2) {
OUTREG(FPB0, pI830->saveFPB0);
OUTREG(FPB1, pI830->saveFPB1);
- OUTREG(DPLL_B, pI830->saveDPLL_B);
if (IS_I965G(pI830))
OUTREG(DPLL_B_MD, pI830->saveDPLL_B_MD);
+ if (pI830->saveDPLL_B & DPLL_VCO_ENABLE)
+ {
+ OUTREG(DPLL_A, pI830->saveDPLL_B & ~DPLL_VCO_ENABLE);
+ usleep(150);
+ }
+ OUTREG(DPLL_B, pI830->saveDPLL_B);
}
/* Wait for clocks to stabilize */
usleep(150);