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author | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-03-20 11:34:40 +0800 |
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committer | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-03-20 11:34:40 +0800 |
commit | 0a612e7115ff993bb8e9a00df13c0b0d20122fd6 (patch) | |
tree | 30cdce5d6cae50261e72cbd26bf81ff0ccda5e21 /src/i830_lvds.c | |
parent | 8bb677889d3f71cde671f17a3589939acad2c3b3 (diff) | |
parent | 4c4faf260eb4dad1b1919c6168fa9ef477b98a39 (diff) |
Merge branch 'master' of git://proxy.ims.intel.com:9419/git/xorg/driver/xf86-video-intel into crestline
Conflicts:
src/i830_display.c
Change LVDS output and postread like upstream. This might
need to be retested on 965GM LVDS.
Diffstat (limited to 'src/i830_lvds.c')
-rw-r--r-- | src/i830_lvds.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/i830_lvds.c b/src/i830_lvds.c index 93243166..23b61f28 100644 --- a/src/i830_lvds.c +++ b/src/i830_lvds.c @@ -225,13 +225,9 @@ i830_lvds_mode_set(xf86OutputPtr output, DisplayModePtr mode, I830Ptr pI830 = I830PTR(pScrn); CARD32 pfit_control; -#if 0 - /* The LVDS pin pair needs to be on before the DPLLs are enabled. - * This is an exception to the general rule that mode_set doesn't turn - * things on. + /* The LVDS pin pair will already have been turned on in the + * i830_crtc_mode_set since it has a large impact on the DPLL settings. */ - OUTREG(LVDS, INREG(LVDS) | LVDS_PORT_EN | LVDS_PIPEB_SELECT); -#endif /* Enable automatic panel scaling so that non-native modes fill the * screen. Should be enabled before the pipe is enabled, according to |