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| author | Jesse Barnes <jbarnes@nietzche.virtuousgeek.org> | 2007-07-02 15:42:02 -0700 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@nietzche.virtuousgeek.org> | 2007-07-02 15:42:02 -0700 |
| commit | f02036aedcd7866c567a6adc070eda3dad872105 (patch) | |
| tree | b8ddd2653006398c7911ac91c01f8d24f6b61862 /src/i830_reg.h | |
| parent | b384c608978dcd3d2ea6c0018179673cb4735f4c (diff) | |
Framebuffer compression changes:
- move FBC register definitions to i830_reg.h
- add fix from Arjan for 965 depth buffer tiling
- add VT switch and clear-at-server-start code for FBC registers
Diffstat (limited to 'src/i830_reg.h')
| -rw-r--r-- | src/i830_reg.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/i830_reg.h b/src/i830_reg.h index 7a8df9f8..b5fa1b98 100644 --- a/src/i830_reg.h +++ b/src/i830_reg.h @@ -29,6 +29,29 @@ #ifndef _I830_REG_H_ #define _I830_REG_H_ +/* Framebuffer compression */ +#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ +#define FBC_LL_BASE 0x03204 /* 4k page aligned */ +#define FBC_CONTROL 0x03208 +#define FBC_CTL_EN (1<<31) +#define FBC_CTL_PERIODIC (1<<30) +#define FBC_CTL_INTERVAL_SHIFT (16) +#define FBC_CTL_STRIDE_SHIFT (5) +#define FBC_CTL_FENCENO (1<<0) +#define FBC_COMMAND 0x0320c +#define FBC_CMD_COMPRESS (1<<0) +#define FBC_STATUS 0x03210 +#define FBC_STAT_COMPRESSING (1<<31) +#define FBC_STAT_COMPRESSED (1<<30) +#define FBC_STAT_MODIFIED (1<<29) +#define FBC_STAT_CURRENT_LINE (1<<0) +#define FBC_CONTROL2 0x03214 +#define FBC_CTL_CPU_FENCE (1<<1) +#define FBC_CTL_PIPEA (0<<0) +#define FBC_CTL_PIPEB (1<<0) + +#define FBC_COMPRESSED_LINES (1536+32) + #define I830_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) #define CMD_3D (0x3<<29) |